From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EBA5FE7716B for ; Wed, 4 Dec 2024 14:52:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/G7WIYcRwTna+e44Dk11rCyDR2M/KGVbXU1R6K7+PZs=; b=xJN8I6cXoFYjRc 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2024 14:52:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733323958; bh=q1EI/ZvprzWeZhl8skF4PiVduPC/wxv9wUqtG/H4t0A=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=fb/f6ieaBtCN8GEiop0yP175EUVy7Pn3gw34bWjj9fQuqnYC49cUEfsV8iGyiAghi KVWPFvAEp/hKopU+K5jgI9gffGx8mifzIK5eQJIa4NQKvDx8YUDkJgFzIquR94ylYr DJjGW/wFTDCzU/ivgUpcRShAsap5DCtpdybeflUAOt/Ruwa4IVPLbsKU8Bf3WyX3wh 8Xp5NuczD6FpmRyZx8a//ssvoTRHiBIJtaVaDYTyTLGGYO5aCvvBHRLW1EkpxxvAaV ejzhGvSC1zxljUXjXYxwskNLGQu2YPu8wJxfZRdAtpEM8IcKIn//sRWCFcEABviwqP UzKkrqejgQQyw== Date: Wed, 4 Dec 2024 08:52:36 -0600 From: Rob Herring To: Valentina Fernandez Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, conor.dooley@microchip.com, conor+dt@kernel.org, jassisinghbrar@gmail.com, krzk+dt@kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v5 3/4] dt-bindings: mailbox: add binding for Microchip IPC mailbox controller Message-ID: <20241204145236.GA202257-robh@kernel.org> References: <20241202141107.193809-1-valentina.fernandezalanis@microchip.com> <20241202141107.193809-4-valentina.fernandezalanis@microchip.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20241202141107.193809-4-valentina.fernandezalanis@microchip.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241204_065239_706046_BC5611A6 X-CRM114-Status: GOOD ( 21.05 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gTW9uLCBEZWMgMDIsIDIwMjQgYXQgMDI6MTE6MDZQTSArMDAwMCwgVmFsZW50aW5hIEZlcm5h bmRleiB3cm90ZToKPiBBZGQgYSBkdC1iaW5kaW5nIGZvciB0aGUgTWljcm9jaGlwIEludGVyLVBy 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233CDC4CECD; Wed, 4 Dec 2024 14:52:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733323958; bh=q1EI/ZvprzWeZhl8skF4PiVduPC/wxv9wUqtG/H4t0A=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=fb/f6ieaBtCN8GEiop0yP175EUVy7Pn3gw34bWjj9fQuqnYC49cUEfsV8iGyiAghi KVWPFvAEp/hKopU+K5jgI9gffGx8mifzIK5eQJIa4NQKvDx8YUDkJgFzIquR94ylYr DJjGW/wFTDCzU/ivgUpcRShAsap5DCtpdybeflUAOt/Ruwa4IVPLbsKU8Bf3WyX3wh 8Xp5NuczD6FpmRyZx8a//ssvoTRHiBIJtaVaDYTyTLGGYO5aCvvBHRLW1EkpxxvAaV ejzhGvSC1zxljUXjXYxwskNLGQu2YPu8wJxfZRdAtpEM8IcKIn//sRWCFcEABviwqP UzKkrqejgQQyw== Date: Wed, 4 Dec 2024 08:52:36 -0600 From: Rob Herring To: Valentina Fernandez Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, conor.dooley@microchip.com, conor+dt@kernel.org, jassisinghbrar@gmail.com, krzk+dt@kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v5 3/4] dt-bindings: mailbox: add binding for Microchip IPC mailbox controller Message-ID: <20241204145236.GA202257-robh@kernel.org> References: <20241202141107.193809-1-valentina.fernandezalanis@microchip.com> <20241202141107.193809-4-valentina.fernandezalanis@microchip.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241202141107.193809-4-valentina.fernandezalanis@microchip.com> On Mon, Dec 02, 2024 at 02:11:06PM +0000, Valentina Fernandez wrote: > Add a dt-binding for the Microchip Inter-Processor Communication (IPC) > mailbox controller. > > Signed-off-by: Valentina Fernandez > --- > .../bindings/mailbox/microchip,sbi-ipc.yaml | 117 ++++++++++++++++++ > 1 file changed, 117 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml > > diff --git a/Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml b/Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml > new file mode 100644 > index 000000000000..e104573d45c1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml > @@ -0,0 +1,117 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mailbox/microchip,sbi-ipc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip Inter-processor communication (IPC) mailbox controller > + > +maintainers: > + - Valentina Fernandez > + > +description: > + The Microchip Inter-processor Communication (IPC) facilitates > + message passing between processors using an interrupt signaling > + mechanism. > + > +properties: > + compatible: > + oneOf: > + - description: > + Intended for use by software running in supervisor privileged > + mode (s-mode). This SBI interface is compatible with the Mi-V > + Inter-hart Communication (IHC) IP. > + const: microchip,sbi-ipc > + > + - description: > + Intended for use by the SBI implementation in machine mode > + (m-mode), this compatible string is for the MIV_IHC Soft-IP. > + const: microchip,miv-ihc-rtl-v2 > + > + reg: > + maxItems: 1 > + > + interrupts: > + minItems: 1 > + maxItems: 5 > + > + interrupt-names: > + minItems: 1 > + maxItems: 5 > + items: > + enum: > + - hart-0 > + - hart-1 > + - hart-2 > + - hart-3 > + - hart-4 > + - hart-5 I don't know why Krzysztof said to list them, when all you needed to do was drop the '+': pattern: "^hart-[0-5]$" > + > + "#mbox-cells": > + description: > > + For "microchip,sbi-ipc", the cell represents the global "logical" > + channel IDs. The meaning of channel IDs are platform firmware dependent. > + > + For "microchip,miv-ihc-rtl-v2", the cell represents the physical > + channel and does not vary based on the platform firmware. > + const: 1 > + > + microchip,ihc-chan-disabled-mask: > + description: > > + Represents the enable/disable state of the bi-directional IHC > + channels within the MIV-IHC IP configuration. > + > + A bit set to '1' indicates that the corresponding channel is disabled, > + and any read or write operations to that channel will return zero. > + > + A bit set to '0' indicates that the corresponding channel is enabled > + and will be accessible through its dedicated address range registers. > + > + The actual enable/disable state of each channel is determined by the > + IP block’s configuration. > + $ref: /schemas/types.yaml#/definitions/uint16 > + maximum: 0x7fff > + default: 0 > + > +required: > + - compatible > + - interrupts > + - interrupt-names > + - "#mbox-cells" > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: microchip,sbi-ipc > + then: > + properties: > + reg: false How do you address the question about this? Add an explanation in the schema. No one is going to remember an answer in a review thread. IOW, assume that we don't remember the answer and will just ask the same questions again. You can do something like: reg: not: description: ... or reg: not: {} description: ... Rob