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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3862f02f5c3sm1151942f8f.65.2024.12.06.08.31.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Dec 2024 08:31:11 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Himanshu Chauhan , Anup Patel , Xu Lu , Atish Patra Subject: [PATCH v3 3/4] drivers: firmware: add riscv SSE support Date: Fri, 6 Dec 2024 17:30:59 +0100 Message-ID: <20241206163102.843505-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241206163102.843505-1-cleger@rivosinc.com> References: <20241206163102.843505-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241206_083114_151797_26807F6E X-CRM114-Status: GOOD ( 24.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add driver level interface to use RISC-V SSE arch support. This interface allows registering SSE handlers, and receive them. This will be used by PMU and GHES driver. Signed-off-by: Himanshu Chauhan Co-developed-by: Himanshu Chauhan Signed-off-by: Clément Léger --- MAINTAINERS | 14 + drivers/firmware/Kconfig | 1 + drivers/firmware/Makefile | 1 + drivers/firmware/riscv/Kconfig | 15 + drivers/firmware/riscv/Makefile | 3 + drivers/firmware/riscv/riscv_sse.c | 691 +++++++++++++++++++++++++++++ include/linux/riscv_sse.h | 56 +++ 7 files changed, 781 insertions(+) create mode 100644 drivers/firmware/riscv/Kconfig create mode 100644 drivers/firmware/riscv/Makefile create mode 100644 drivers/firmware/riscv/riscv_sse.c create mode 100644 include/linux/riscv_sse.h diff --git a/MAINTAINERS b/MAINTAINERS index 686109008d8e..a3ddde7fe9fb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20125,6 +20125,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux.git F: Documentation/devicetree/bindings/iommu/riscv,iommu.yaml F: drivers/iommu/riscv/ +RISC-V FIRMWARE DRIVERS +M: Conor Dooley +L: linux-riscv@lists.infradead.org +S: Maintained +T: git git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git +F: drivers/firmware/riscv/* + RISC-V MICROCHIP FPGA SUPPORT M: Conor Dooley M: Daire McNamara @@ -20177,6 +20184,13 @@ F: drivers/perf/riscv_pmu.c F: drivers/perf/riscv_pmu_legacy.c F: drivers/perf/riscv_pmu_sbi.c +RISC-V SSE DRIVER +M: Clément Léger +L: linux-riscv@lists.infradead.org +S: Maintained +F: drivers/firmware/riscv/riscv_sse.c +F: include/linux/riscv_sse.h + RISC-V THEAD SoC SUPPORT M: Drew Fustini M: Guo Ren diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 71d8b26c4103..9e996a1fd511 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -267,6 +267,7 @@ source "drivers/firmware/meson/Kconfig" source "drivers/firmware/microchip/Kconfig" source "drivers/firmware/psci/Kconfig" source "drivers/firmware/qcom/Kconfig" +source "drivers/firmware/riscv/Kconfig" source "drivers/firmware/smccc/Kconfig" source "drivers/firmware/tegra/Kconfig" source "drivers/firmware/xilinx/Kconfig" diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index 7a8d486e718f..c0f5009949a8 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -33,6 +33,7 @@ obj-y += efi/ obj-y += imx/ obj-y += psci/ obj-y += qcom/ +obj-y += riscv/ obj-y += smccc/ obj-y += tegra/ obj-y += xilinx/ diff --git a/drivers/firmware/riscv/Kconfig b/drivers/firmware/riscv/Kconfig new file mode 100644 index 000000000000..8056ed3262d9 --- /dev/null +++ b/drivers/firmware/riscv/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "Risc-V Specific firmware drivers" +depends on RISCV + +config RISCV_SSE + bool "Enable SBI Supervisor Software Events support" + depends on RISCV_SBI + default y + help + The Supervisor Software Events support allow the SBI to deliver + NMI-like notifications to the supervisor mode software. When enable, + this option provides support to register callbacks on specific SSE + events. + +endmenu diff --git a/drivers/firmware/riscv/Makefile b/drivers/firmware/riscv/Makefile new file mode 100644 index 000000000000..4ccfcbbc28ea --- /dev/null +++ b/drivers/firmware/riscv/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_RISCV_SSE) += riscv_sse.o diff --git a/drivers/firmware/riscv/riscv_sse.c b/drivers/firmware/riscv/riscv_sse.c new file mode 100644 index 000000000000..c165e32cc9a5 --- /dev/null +++ b/drivers/firmware/riscv/riscv_sse.c @@ -0,0 +1,691 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024 Rivos Inc. + */ + +#define pr_fmt(fmt) "sse: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +struct sse_event { + struct list_head list; + u32 evt; + u32 priority; + sse_event_handler *handler; + void *handler_arg; + bool is_enabled; + /* Only valid for global events */ + unsigned int cpu; + + union { + struct sse_registered_event *global; + struct sse_registered_event __percpu *local; + }; +}; + +static int sse_hp_state; +static bool sse_available; +static DEFINE_SPINLOCK(events_list_lock); +static LIST_HEAD(events); +static DEFINE_MUTEX(sse_mutex); + +struct sse_registered_event { + struct sse_event_arch_data arch; + struct sse_event *evt; + unsigned long attr_buf; +}; + +void sse_handle_event(struct sse_event_arch_data *arch_event, + struct pt_regs *regs) +{ + int ret; + struct sse_registered_event *reg_evt = + container_of(arch_event, struct sse_registered_event, arch); + struct sse_event *evt = reg_evt->evt; + + ret = evt->handler(evt->evt, evt->handler_arg, regs); + if (ret) + pr_warn("event %x handler failed with error %d\n", evt->evt, + ret); +} + +static bool sse_event_is_global(u32 evt) +{ + return !!(evt & SBI_SSE_EVENT_GLOBAL); +} + +static +struct sse_event *sse_event_get(u32 evt) +{ + struct sse_event *sse_evt = NULL, *tmp; + + scoped_guard(spinlock, &events_list_lock) { + list_for_each_entry(tmp, &events, list) { + if (tmp->evt == evt) { + return sse_evt; + } + } + } + + return NULL; +} + +static phys_addr_t sse_event_get_phys(struct sse_registered_event *reg_evt, + void *addr) +{ + phys_addr_t phys; + + if (sse_event_is_global(reg_evt->evt->evt)) + phys = virt_to_phys(addr); + else + phys = per_cpu_ptr_to_phys(addr); + + return phys; +} + +static int sse_sbi_event_func(struct sse_event *event, unsigned long func) +{ + struct sbiret ret; + u32 evt = event->evt; + + ret = sbi_ecall(SBI_EXT_SSE, func, evt, 0, 0, 0, 0, 0); + if (ret.error) + pr_debug("Failed to execute func %lx, event %x, error %ld\n", + func, evt, ret.error); + + return sbi_err_map_linux_errno(ret.error); +} + +static int sse_sbi_disable_event(struct sse_event *event) +{ + return sse_sbi_event_func(event, SBI_SSE_EVENT_DISABLE); +} + +static int sse_sbi_enable_event(struct sse_event *event) +{ + return sse_sbi_event_func(event, SBI_SSE_EVENT_ENABLE); +} + +static int sse_event_attr_get_no_lock(struct sse_registered_event *reg_evt, + unsigned long attr_id, unsigned long *val) +{ + struct sbiret sret; + u32 evt = reg_evt->evt->evt; + unsigned long phys; + + phys = sse_event_get_phys(reg_evt, ®_evt->attr_buf); + + sret = sbi_ecall(SBI_EXT_SSE, SBI_SSE_EVENT_ATTR_READ, evt, + attr_id, 1, phys, 0, 0); + if (sret.error) { + pr_debug("Failed to get event %x attr %lx, error %ld\n", evt, + attr_id, sret.error); + return sbi_err_map_linux_errno(sret.error); + } + + *val = reg_evt->attr_buf; + + return 0; +} + +static int sse_event_attr_set_nolock(struct sse_registered_event *reg_evt, + unsigned long attr_id, unsigned long val) +{ + struct sbiret sret; + u32 evt = reg_evt->evt->evt; + unsigned long phys; + + reg_evt->attr_buf = val; + phys = sse_event_get_phys(reg_evt, ®_evt->attr_buf); + + sret = sbi_ecall(SBI_EXT_SSE, SBI_SSE_EVENT_ATTR_WRITE, evt, + attr_id, 1, phys, 0, 0); + if (sret.error && sret.error != SBI_ERR_INVALID_STATE) { + pr_debug("Failed to set event %x attr %lx, error %ld\n", evt, + attr_id, sret.error); + return sbi_err_map_linux_errno(sret.error); + } + + return 0; +} + +static int sse_event_set_target_cpu_nolock(struct sse_event *event, + unsigned int cpu) +{ + unsigned int hart_id = cpuid_to_hartid_map(cpu); + struct sse_registered_event *reg_evt = event->global; + u32 evt = event->evt; + bool was_enabled; + int ret; + + if (!sse_event_is_global(evt)) + return -EINVAL; + + was_enabled = event->is_enabled; + if (was_enabled) + sse_sbi_disable_event(event); + do { + ret = sse_event_attr_set_nolock(reg_evt, + SBI_SSE_ATTR_PREFERRED_HART, + hart_id); + } while (ret == -EINVAL); + + if (ret == 0) + event->cpu = cpu; + + if (was_enabled) + sse_sbi_enable_event(event); + + return 0; +} + +int sse_event_set_target_cpu(struct sse_event *event, unsigned int cpu) +{ + int ret; + + scoped_guard(mutex, &sse_mutex) { + cpus_read_lock(); + + if (!cpu_online(cpu)) + return -EINVAL; + + ret = sse_event_set_target_cpu_nolock(event, cpu); + + cpus_read_unlock(); + } + + return ret; +} + +static int sse_event_init_registered(unsigned int cpu, + struct sse_registered_event *reg_evt, + struct sse_event *event) +{ + reg_evt->evt = event; + arch_sse_init_event(®_evt->arch, event->evt, cpu); + + return 0; +} + +static void sse_event_free_registered(struct sse_registered_event *reg_evt) +{ + arch_sse_free_event(®_evt->arch); +} + +static int sse_event_alloc_global(struct sse_event *event) +{ + int err; + struct sse_registered_event *reg_evt; + + reg_evt = kzalloc(sizeof(*reg_evt), GFP_KERNEL); + if (!reg_evt) + return -ENOMEM; + + event->global = reg_evt; + err = sse_event_init_registered(smp_processor_id(), reg_evt, + event); + if (err) + kfree(reg_evt); + + return err; +} + +static int sse_event_alloc_local(struct sse_event *event) +{ + int err; + unsigned int cpu, err_cpu; + struct sse_registered_event *reg_evt; + struct sse_registered_event __percpu *reg_evts; + + reg_evts = alloc_percpu(struct sse_registered_event); + if (!reg_evts) + return -ENOMEM; + + event->local = reg_evts; + + for_each_possible_cpu(cpu) { + reg_evt = per_cpu_ptr(reg_evts, cpu); + err = sse_event_init_registered(cpu, reg_evt, event); + if (err) { + err_cpu = cpu; + goto err_free_per_cpu; + } + } + + return 0; + +err_free_per_cpu: + for_each_possible_cpu(cpu) { + if (cpu == err_cpu) + break; + reg_evt = per_cpu_ptr(reg_evts, cpu); + sse_event_free_registered(reg_evt); + } + + free_percpu(reg_evts); + + return err; +} + +static struct sse_event *sse_event_alloc(u32 evt, + u32 priority, + sse_event_handler *handler, void *arg) +{ + int err; + struct sse_event *event; + + event = kzalloc(sizeof(*event), GFP_KERNEL); + if (!event) + return ERR_PTR(-ENOMEM); + + event->evt = evt; + event->priority = priority; + event->handler_arg = arg; + event->handler = handler; + + if (sse_event_is_global(evt)) { + err = sse_event_alloc_global(event); + if (err) + goto err_alloc_reg_evt; + } else { + err = sse_event_alloc_local(event); + if (err) + goto err_alloc_reg_evt; + } + + return event; + +err_alloc_reg_evt: + kfree(event); + + return ERR_PTR(err); +} + +static int sse_sbi_register_event(struct sse_event *event, + struct sse_registered_event *reg_evt) +{ + int ret; + + ret = sse_event_attr_set_nolock(reg_evt, SBI_SSE_ATTR_PRIO, + event->priority); + if (ret) + return ret; + + return arch_sse_register_event(®_evt->arch); +} + +static int sse_event_register_local(struct sse_event *event) +{ + int ret; + struct sse_registered_event *reg_evt = per_cpu_ptr(event->local, + smp_processor_id()); + + ret = sse_sbi_register_event(event, reg_evt); + if (ret) + pr_debug("Failed to register event %x: err %d\n", event->evt, + ret); + + return ret; +} + + +static int sse_sbi_unregister_event(struct sse_event *event) +{ + return sse_sbi_event_func(event, SBI_SSE_EVENT_UNREGISTER); +} + +struct sse_per_cpu_evt { + struct sse_event *event; + unsigned long func; + atomic_t error; +}; + +static void sse_event_per_cpu_func(void *info) +{ + int ret; + struct sse_per_cpu_evt *cpu_evt = info; + + if (cpu_evt->func == SBI_SSE_EVENT_REGISTER) + ret = sse_event_register_local(cpu_evt->event); + else + ret = sse_sbi_event_func(cpu_evt->event, cpu_evt->func); + + if (ret) + atomic_set(&cpu_evt->error, ret); +} + +static void sse_event_free(struct sse_event *event) +{ + unsigned int cpu; + struct sse_registered_event *reg_evt; + + if (sse_event_is_global(event->evt)) { + sse_event_free_registered(event->global); + kfree(event->global); + } else { + for_each_possible_cpu(cpu) { + reg_evt = per_cpu_ptr(event->local, cpu); + sse_event_free_registered(reg_evt); + } + free_percpu(event->local); + } + + kfree(event); +} + +int sse_event_enable(struct sse_event *event) +{ + int ret = 0; + struct sse_per_cpu_evt cpu_evt; + + scoped_guard(mutex, &sse_mutex) { + cpus_read_lock(); + if (sse_event_is_global(event->evt)) { + ret = sse_sbi_enable_event(event); + } else { + cpu_evt.event = event; + atomic_set(&cpu_evt.error, 0); + cpu_evt.func = SBI_SSE_EVENT_ENABLE; + on_each_cpu(sse_event_per_cpu_func, &cpu_evt, 1); + ret = atomic_read(&cpu_evt.error); + if (ret) { + cpu_evt.func = SBI_SSE_EVENT_DISABLE; + on_each_cpu(sse_event_per_cpu_func, &cpu_evt, + 1); + } + } + cpus_read_unlock(); + + if (ret == 0) + event->is_enabled = true; + } + + return ret; +} + +static void sse_events_mask(void) +{ + sbi_ecall(SBI_EXT_SSE, SBI_SSE_EVENT_HART_MASK, 0, 0, 0, 0, 0, 0); +} + +static void sse_events_unmask(void) +{ + sbi_ecall(SBI_EXT_SSE, SBI_SSE_EVENT_HART_UNMASK, 0, 0, 0, 0, 0, 0); +} + +static void sse_event_disable_nolock(struct sse_event *event) +{ + struct sse_per_cpu_evt cpu_evt; + + if (sse_event_is_global(event->evt)) { + sse_sbi_disable_event(event); + } else { + cpu_evt.event = event; + cpu_evt.func = SBI_SSE_EVENT_DISABLE; + on_each_cpu(sse_event_per_cpu_func, &cpu_evt, 1); + } +} + +void sse_event_disable(struct sse_event *event) +{ + scoped_guard(mutex, &sse_mutex) { + cpus_read_lock(); + sse_event_disable_nolock(event); + event->is_enabled = false; + cpus_read_unlock(); + } +} + +struct sse_event *sse_event_register(u32 evt, u32 priority, + sse_event_handler *handler, void *arg) +{ + struct sse_per_cpu_evt cpu_evt; + struct sse_event *event; + int ret = 0; + + if (!sse_available) + return ERR_PTR(-EOPNOTSUPP); + + mutex_lock(&sse_mutex); + if (sse_event_get(evt)) { + pr_debug("Event %x already registered\n", evt); + ret = -EEXIST; + goto out_unlock; + } + + event = sse_event_alloc(evt, priority, handler, arg); + if (IS_ERR(event)) { + ret = PTR_ERR(event); + goto out_unlock; + } + + cpus_read_lock(); + if (sse_event_is_global(evt)) { + unsigned long preferred_hart; + + ret = sse_event_attr_get_no_lock(event->global, + SBI_SSE_ATTR_PREFERRED_HART, + &preferred_hart); + if (ret) + goto err_event_free; + event->cpu = riscv_hartid_to_cpuid(preferred_hart); + + ret = sse_sbi_register_event(event, event->global); + if (ret) + goto err_event_free; + + } else { + cpu_evt.event = event; + atomic_set(&cpu_evt.error, 0); + cpu_evt.func = SBI_SSE_EVENT_REGISTER; + on_each_cpu(sse_event_per_cpu_func, &cpu_evt, 1); + ret = atomic_read(&cpu_evt.error); + if (ret) { + cpu_evt.func = SBI_SSE_EVENT_UNREGISTER; + on_each_cpu(sse_event_per_cpu_func, &cpu_evt, 1); + goto err_event_free; + } + } + cpus_read_unlock(); + + scoped_guard(spinlock, &events_list_lock) + list_add(&event->list, &events); + + mutex_unlock(&sse_mutex); + + return event; + +err_event_free: + cpus_read_unlock(); + sse_event_free(event); +out_unlock: + mutex_unlock(&sse_mutex); + + return ERR_PTR(ret); +} + +static void sse_event_unregister_nolock(struct sse_event *event) +{ + struct sse_per_cpu_evt cpu_evt; + + if (sse_event_is_global(event->evt)) { + sse_sbi_unregister_event(event); + } else { + cpu_evt.event = event; + cpu_evt.func = SBI_SSE_EVENT_UNREGISTER; + on_each_cpu(sse_event_per_cpu_func, &cpu_evt, 1); + } +} + +void sse_event_unregister(struct sse_event *event) +{ + scoped_guard(mutex, &sse_mutex) { + cpus_read_lock(); + sse_event_unregister_nolock(event); + cpus_read_unlock(); + + scoped_guard(spinlock, &events_list_lock) + list_del(&event->list); + + sse_event_free(event); + } +} + +static int sse_cpu_online(unsigned int cpu) +{ + struct sse_event *sse_evt; + + scoped_guard(spinlock, &events_list_lock) { + list_for_each_entry(sse_evt, &events, list) { + if (sse_event_is_global(sse_evt->evt)) + continue; + + sse_event_register_local(sse_evt); + if (sse_evt->is_enabled) + sse_sbi_enable_event(sse_evt); + } + } + + /* Ready to handle events. Unmask SSE. */ + sse_events_unmask(); + + return 0; +} + +static int sse_cpu_teardown(unsigned int cpu) +{ + unsigned int next_cpu; + struct sse_event *sse_evt; + + /* Mask the sse events */ + sse_events_mask(); + + scoped_guard(spinlock, &events_list_lock) { + list_for_each_entry(sse_evt, &events, list) { + if (!sse_event_is_global(sse_evt->evt)) { + + if (sse_evt->is_enabled) + sse_sbi_disable_event(sse_evt); + + sse_sbi_unregister_event(sse_evt); + continue; + } + + if (sse_evt->cpu != smp_processor_id()) + continue; + + /* Update destination hart for global event */ + next_cpu = cpumask_any_but(cpu_online_mask, cpu); + sse_event_set_target_cpu_nolock(sse_evt, next_cpu); + } + } + + return 0; +} + +static void sse_reset(void) +{ + struct sse_event *event = NULL; + + list_for_each_entry(event, &events, list) { + sse_event_disable_nolock(event); + sse_event_unregister_nolock(event); + } +} + +static int sse_pm_notifier(struct notifier_block *nb, unsigned long action, + void *data) +{ + WARN_ON_ONCE(preemptible()); + + switch (action) { + case CPU_PM_ENTER: + sse_events_mask(); + break; + case CPU_PM_EXIT: + case CPU_PM_ENTER_FAILED: + sse_events_unmask(); + break; + default: + return NOTIFY_DONE; + } + + return NOTIFY_OK; +} + +static struct notifier_block sse_pm_nb = { + .notifier_call = sse_pm_notifier, +}; + +/* + * Mask all CPUs and unregister all events on panic, reboot or kexec. + */ +static int sse_reboot_notifier(struct notifier_block *nb, unsigned long action, + void *data) +{ + cpuhp_remove_state(sse_hp_state); + + sse_reset(); + + return NOTIFY_OK; +} + +static struct notifier_block sse_reboot_nb = { + .notifier_call = sse_reboot_notifier, +}; + +static int __init sse_init(void) +{ + int cpu, ret; + + if (sbi_probe_extension(SBI_EXT_SSE) <= 0) { + pr_err("Missing SBI SSE extension\n"); + return -EOPNOTSUPP; + } + pr_info("SBI SSE extension detected\n"); + + for_each_possible_cpu(cpu) + INIT_LIST_HEAD(&events); + + ret = cpu_pm_register_notifier(&sse_pm_nb); + if (ret) { + pr_warn("Failed to register CPU PM notifier...\n"); + return ret; + } + + ret = register_reboot_notifier(&sse_reboot_nb); + if (ret) { + pr_warn("Failed to register reboot notifier...\n"); + goto remove_cpupm; + } + + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/sse:online", + sse_cpu_online, sse_cpu_teardown); + if (ret < 0) + goto remove_reboot; + + sse_hp_state = ret; + sse_available = true; + + return 0; + +remove_reboot: + unregister_reboot_notifier(&sse_reboot_nb); + +remove_cpupm: + cpu_pm_unregister_notifier(&sse_pm_nb); + + return ret; +} +arch_initcall(sse_init); diff --git a/include/linux/riscv_sse.h b/include/linux/riscv_sse.h new file mode 100644 index 000000000000..c73184074b8c --- /dev/null +++ b/include/linux/riscv_sse.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Rivos Inc. + */ + +#ifndef __LINUX_RISCV_SSE_H +#define __LINUX_RISCV_SSE_H + +#include +#include + +struct sse_event; +struct pt_regs; + +typedef int (sse_event_handler)(u32 event_num, void *arg, struct pt_regs *regs); + +#ifdef CONFIG_RISCV_SSE + +struct sse_event *sse_event_register(u32 event_num, u32 priority, + sse_event_handler *handler, void *arg); + +void sse_event_unregister(struct sse_event *evt); + +int sse_event_set_target_cpu(struct sse_event *sse_evt, unsigned int cpu); + +int sse_event_enable(struct sse_event *sse_evt); + +void sse_event_disable(struct sse_event *sse_evt); + +#else +static inline struct sse_event *sse_event_register(u32 event_num, u32 priority, + sse_event_handler *handler, + void *arg) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static inline void sse_event_unregister(struct sse_event *evt) {} + +static inline int sse_event_set_target_cpu(struct sse_event *sse_evt, + unsigned int cpu) +{ + return -EOPNOTSUPP; +} + +static inline int sse_event_enable(struct sse_event *sse_evt) +{ + return -EOPNOTSUPP; +} + +static inline void sse_event_disable(struct sse_event *sse_evt) {} + + +#endif + +#endif /* __LINUX_RISCV_SSE_H */ -- 2.45.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 462B9E77173 for ; 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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org QWRkIGRyaXZlciBsZXZlbCBpbnRlcmZhY2UgdG8gdXNlIFJJU0MtViBTU0UgYXJjaCBzdXBwb3J0 LiBUaGlzIGludGVyZmFjZQphbGxvd3MgcmVnaXN0ZXJpbmcgU1NFIGhhbmRsZXJzLCBhbmQgcmVj ZWl2ZSB0aGVtLiBUaGlzIHdpbGwgYmUgdXNlZCBieQpQTVUgYW5kIEdIRVMgZHJpdmVyLgoKU2ln bmVkLW9mZi1ieTogSGltYW5zaHUgQ2hhdWhhbiA8aGNoYXVoYW5AdmVudGFuYW1pY3JvLmNvbT4K Q28tZGV2ZWxvcGVkLWJ5OiBIaW1hbnNodSBDaGF1aGFuIDxoY2hhdWhhbkB2ZW50YW5hbWljcm8u Y29tPgpTaWduZWQtb2ZmLWJ5OiBDbMOpbWVudCBMw6lnZXIgPGNsZWdlckByaXZvc2luYy5jb20+ Ci0tLQogTUFJTlRBSU5FUlMgICAgICAgICAgICAgICAgICAgICAgICB8ICAxNCArCiBkcml2ZXJz L2Zpcm13YXJlL0tjb25maWcgICAgICAgICAgIHwgICAxICsKIGRyaXZlcnMvZmlybXdhcmUvTWFr ZWZpbGUgICAgICAgICAgfCAgIDEgKwogZHJpdmVycy9maXJtd2FyZS9yaXNjdi9LY29uZmlnICAg ICB8ICAxNSArCiBkcml2ZXJzL2Zpcm13YXJlL3Jpc2N2L01ha2VmaWxlICAgIHwgICAzICsKIGRy aXZlcnMvZmlybXdhcmUvcmlzY3YvcmlzY3Zfc3NlLmMgfCA2OTEgKysrKysrKysrKysrKysrKysr KysrKysrKysrKysKIGluY2x1ZGUvbGludXgvcmlzY3Zfc3NlLmggICAgICAgICAgfCAgNTYgKysr CiA3IGZpbGVzIGNoYW5nZWQsIDc4MSBpbnNlcnRpb25zKCspCiBjcmVhdGUgbW9kZSAxMDA2NDQg ZHJpdmVycy9maXJtd2FyZS9yaXNjdi9LY29uZmlnCiBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVy cy9maXJtd2FyZS9yaXNjdi9NYWtlZmlsZQogY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvZmly bXdhcmUvcmlzY3YvcmlzY3Zfc3NlLmMKIGNyZWF0ZSBtb2RlIDEwMDY0NCBpbmNsdWRlL2xpbnV4 L3Jpc2N2X3NzZS5oCgpkaWZmIC0tZ2l0IGEvTUFJTlRBSU5FUlMgYi9NQUlOVEFJTkVSUwppbmRl eCA2ODYxMDkwMDhkOGUuLmEzZGRkZTdmZTlmYiAxMDA2NDQKLS0tIGEvTUFJTlRBSU5FUlMKKysr IGIvTUFJTlRBSU5FUlMKQEAgLTIwMTI1LDYgKzIwMTI1LDEzIEBAIFQ6CWdpdCBnaXQ6Ly9naXQu a2VybmVsLm9yZy9wdWIvc2NtL2xpbnV4L2tlcm5lbC9naXQvaW9tbXUvbGludXguZ2l0CiBGOglE b2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvaW9tbXUvcmlzY3YsaW9tbXUueWFtbAog RjoJZHJpdmVycy9pb21tdS9yaXNjdi8KIAorUklTQy1WIEZJUk1XQVJFIERSSVZFUlMKK006CUNv bm9yIERvb2xleSA8Y29ub3JAa2VybmVsLm9yZz4KK0w6CWxpbnV4LXJpc2N2QGxpc3RzLmluZnJh ZGVhZC5vcmcKK1M6CU1haW50YWluZWQKK1Q6CWdpdCBnaXQ6Ly9naXQua2VybmVsLm9yZy9wdWIv c2NtL2xpbnV4L2tlcm5lbC9naXQvY29ub3IvbGludXguZ2l0CitGOglkcml2ZXJzL2Zpcm13YXJl L3Jpc2N2LyoKKwogUklTQy1WIE1JQ1JPQ0hJUCBGUEdBIFNVUFBPUlQKIE06CUNvbm9yIERvb2xl eSA8Y29ub3IuZG9vbGV5QG1pY3JvY2hpcC5jb20+CiBNOglEYWlyZSBNY05hbWFyYSA8ZGFpcmUu bWNuYW1hcmFAbWljcm9jaGlwLmNvbT4KQEAgLTIwMTc3LDYgKzIwMTg0LDEzIEBAIEY6CWRyaXZl cnMvcGVyZi9yaXNjdl9wbXUuYwogRjoJZHJpdmVycy9wZXJmL3Jpc2N2X3BtdV9sZWdhY3kuYwog RjoJZHJpdmVycy9wZXJmL3Jpc2N2X3BtdV9zYmkuYwogCitSSVNDLVYgU1NFIERSSVZFUgorTToJ Q2zDqW1lbnQgTMOpZ2VyIDxjbGVnZXJAcml2b3NpbmMuY29tPgorTDoJbGludXgtcmlzY3ZAbGlz dHMuaW5mcmFkZWFkLm9yZworUzoJTWFpbnRhaW5lZAorRjoJZHJpdmVycy9maXJtd2FyZS9yaXNj di9yaXNjdl9zc2UuYworRjoJaW5jbHVkZS9saW51eC9yaXNjdl9zc2UuaAorCiBSSVNDLVYgVEhF QUQgU29DIFNVUFBPUlQKIE06CURyZXcgRnVzdGluaSA8ZHJld0BwZHA3LmNvbT4KIE06CUd1byBS ZW4gPGd1b3JlbkBrZXJuZWwub3JnPgpkaWZmIC0tZ2l0IGEvZHJpdmVycy9maXJtd2FyZS9LY29u ZmlnIGIvZHJpdmVycy9maXJtd2FyZS9LY29uZmlnCmluZGV4IDcxZDhiMjZjNDEwMy4uOWU5OTZh MWZkNTExIDEwMDY0NAotLS0gYS9kcml2ZXJzL2Zpcm13YXJlL0tjb25maWcKKysrIGIvZHJpdmVy cy9maXJtd2FyZS9LY29uZmlnCkBAIC0yNjcsNiArMjY3LDcgQEAgc291cmNlICJkcml2ZXJzL2Zp cm13YXJlL21lc29uL0tjb25maWciCiBzb3VyY2UgImRyaXZlcnMvZmlybXdhcmUvbWljcm9jaGlw L0tjb25maWciCiBzb3VyY2UgImRyaXZlcnMvZmlybXdhcmUvcHNjaS9LY29uZmlnIgogc291cmNl ICJkcml2ZXJzL2Zpcm13YXJlL3Fjb20vS2NvbmZpZyIKK3NvdXJjZSAiZHJpdmVycy9maXJtd2Fy ZS9yaXNjdi9LY29uZmlnIgogc291cmNlICJkcml2ZXJzL2Zpcm13YXJlL3NtY2NjL0tjb25maWci CiBzb3VyY2UgImRyaXZlcnMvZmlybXdhcmUvdGVncmEvS2NvbmZpZyIKIHNvdXJjZSAiZHJpdmVy cy9maXJtd2FyZS94aWxpbngvS2NvbmZpZyIKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZmlybXdhcmUv TWFrZWZpbGUgYi9kcml2ZXJzL2Zpcm13YXJlL01ha2VmaWxlCmluZGV4IDdhOGQ0ODZlNzE4Zi4u YzBmNTAwOTk0OWE4IDEwMDY0NAotLS0gYS9kcml2ZXJzL2Zpcm13YXJlL01ha2VmaWxlCisrKyBi L2RyaXZlcnMvZmlybXdhcmUvTWFrZWZpbGUKQEAgLTMzLDYgKzMzLDcgQEAgb2JqLXkJCQkJKz0g ZWZpLwogb2JqLXkJCQkJKz0gaW14Lwogb2JqLXkJCQkJKz0gcHNjaS8KIG9iai15CQkJCSs9IHFj b20vCitvYmoteQkJCQkrPSByaXNjdi8KIG9iai15CQkJCSs9IHNtY2NjLwogb2JqLXkJCQkJKz0g dGVncmEvCiBvYmoteQkJCQkrPSB4aWxpbngvCmRpZmYgLS1naXQgYS9kcml2ZXJzL2Zpcm13YXJl L3Jpc2N2L0tjb25maWcgYi9kcml2ZXJzL2Zpcm13YXJlL3Jpc2N2L0tjb25maWcKbmV3IGZpbGUg bW9kZSAxMDA2NDQKaW5kZXggMDAwMDAwMDAwMDAwLi44MDU2ZWQzMjYyZDkKLS0tIC9kZXYvbnVs bAorKysgYi9kcml2ZXJzL2Zpcm13YXJlL3Jpc2N2L0tjb25maWcKQEAgLTAsMCArMSwxNSBAQAor IyBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMC1vbmx5CittZW51ICJSaXNjLVYgU3Bl Y2lmaWMgZmlybXdhcmUgZHJpdmVycyIKK2RlcGVuZHMgb24gUklTQ1YKKworY29uZmlnIFJJU0NW X1NTRQorCWJvb2wgIkVuYWJsZSBTQkkgU3VwZXJ2aXNvciBTb2Z0d2FyZSBFdmVudHMgc3VwcG9y dCIKKwlkZXBlbmRzIG9uIFJJU0NWX1NCSQorCWRlZmF1bHQgeQorCWhlbHAKKwkgIFRoZSBTdXBl cnZpc29yIFNvZnR3YXJlIEV2ZW50cyBzdXBwb3J0IGFsbG93IHRoZSBTQkkgdG8gZGVsaXZlcgor CSAgTk1JLWxpa2Ugbm90aWZpY2F0aW9ucyB0byB0aGUgc3VwZXJ2aXNvciBtb2RlIHNvZnR3YXJl LiBXaGVuIGVuYWJsZSwKKwkgIHRoaXMgb3B0aW9uIHByb3ZpZGVzIHN1cHBvcnQgdG8gcmVnaXN0 ZXIgY2FsbGJhY2tzIG9uIHNwZWNpZmljIFNTRQorCSAgZXZlbnRzLgorCitlbmRtZW51CmRpZmYg LS1naXQgYS9kcml2ZXJzL2Zpcm13YXJlL3Jpc2N2L01ha2VmaWxlIGIvZHJpdmVycy9maXJtd2Fy ZS9yaXNjdi9NYWtlZmlsZQpuZXcgZmlsZSBtb2RlIDEwMDY0NAppbmRleCAwMDAwMDAwMDAwMDAu LjRjY2ZjYmJjMjhlYQotLS0gL2Rldi9udWxsCisrKyBiL2RyaXZlcnMvZmlybXdhcmUvcmlzY3Yv TWFrZWZpbGUKQEAgLTAsMCArMSwzIEBACisjIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiBHUEwt Mi4wCisKK29iai0kKENPTkZJR19SSVNDVl9TU0UpCQkrPSByaXNjdl9zc2UubwpkaWZmIC0tZ2l0 IGEvZHJpdmVycy9maXJtd2FyZS9yaXNjdi9yaXNjdl9zc2UuYyBiL2RyaXZlcnMvZmlybXdhcmUv cmlzY3YvcmlzY3Zfc3NlLmMKbmV3IGZpbGUgbW9kZSAxMDA2NDQKaW5kZXggMDAwMDAwMDAwMDAw Li5jMTY1ZTMyY2M5YTUKLS0tIC9kZXYvbnVsbAorKysgYi9kcml2ZXJzL2Zpcm13YXJlL3Jpc2N2 L3Jpc2N2X3NzZS5jCkBAIC0wLDAgKzEsNjkxIEBACisvLyBTUERYLUxpY2Vuc2UtSWRlbnRpZmll cjogR1BMLTIuMC1vbmx5CisvKgorICogQ29weXJpZ2h0IChDKSAyMDI0IFJpdm9zIEluYy4KKyAq LworCisjZGVmaW5lIHByX2ZtdChmbXQpICJzc2U6ICIgZm10CisKKyNpbmNsdWRlIDxsaW51eC9j cHUuaD4KKyNpbmNsdWRlIDxsaW51eC9jcHVob3RwbHVnLmg+CisjaW5jbHVkZSA8bGludXgvY3B1 X3BtLmg+CisjaW5jbHVkZSA8bGludXgvaGFyZGlycS5oPgorI2luY2x1ZGUgPGxpbnV4L2xpc3Qu aD4KKyNpbmNsdWRlIDxsaW51eC9wZXJjcHUtZGVmcy5oPgorI2luY2x1ZGUgPGxpbnV4L3JlYm9v dC5oPgorI2luY2x1ZGUgPGxpbnV4L3Jpc2N2X3NzZS5oPgorI2luY2x1ZGUgPGxpbnV4L3NsYWIu aD4KKworI2luY2x1ZGUgPGFzbS9zYmkuaD4KKyNpbmNsdWRlIDxhc20vc3NlLmg+CisKK3N0cnVj dCBzc2VfZXZlbnQgeworCXN0cnVjdCBsaXN0X2hlYWQgbGlzdDsKKwl1MzIgZXZ0OworCXUzMiBw cmlvcml0eTsKKwlzc2VfZXZlbnRfaGFuZGxlciAqaGFuZGxlcjsKKwl2b2lkICpoYW5kbGVyX2Fy ZzsKKwlib29sIGlzX2VuYWJsZWQ7CisJLyogT25seSB2YWxpZCBmb3IgZ2xvYmFsIGV2ZW50cyAq LworCXVuc2lnbmVkIGludCBjcHU7CisKKwl1bmlvbiB7CisJCXN0cnVjdCBzc2VfcmVnaXN0ZXJl ZF9ldmVudCAqZ2xvYmFsOworCQlzdHJ1Y3Qgc3NlX3JlZ2lzdGVyZWRfZXZlbnQgX19wZXJjcHUg KmxvY2FsOworCX07Cit9OworCitzdGF0aWMgaW50IHNzZV9ocF9zdGF0ZTsKK3N0YXRpYyBib29s IHNzZV9hdmFpbGFibGU7CitzdGF0aWMgREVGSU5FX1NQSU5MT0NLKGV2ZW50c19saXN0X2xvY2sp Oworc3RhdGljIExJU1RfSEVBRChldmVudHMpOworc3RhdGljIERFRklORV9NVVRFWChzc2VfbXV0 ZXgpOworCitzdHJ1Y3Qgc3NlX3JlZ2lzdGVyZWRfZXZlbnQgeworCXN0cnVjdCBzc2VfZXZlbnRf YXJjaF9kYXRhIGFyY2g7CisJc3RydWN0IHNzZV9ldmVudCAqZXZ0OworCXVuc2lnbmVkIGxvbmcg YXR0cl9idWY7Cit9OworCit2b2lkIHNzZV9oYW5kbGVfZXZlbnQoc3RydWN0IHNzZV9ldmVudF9h cmNoX2RhdGEgKmFyY2hfZXZlbnQsCisJCSAgICAgIHN0cnVjdCBwdF9yZWdzICpyZWdzKQorewor CWludCByZXQ7CisJc3RydWN0IHNzZV9yZWdpc3RlcmVkX2V2ZW50ICpyZWdfZXZ0ID0KKwkJY29u dGFpbmVyX29mKGFyY2hfZXZlbnQsIHN0cnVjdCBzc2VfcmVnaXN0ZXJlZF9ldmVudCwgYXJjaCk7 CisJc3RydWN0IHNzZV9ldmVudCAqZXZ0ID0gcmVnX2V2dC0+ZXZ0OworCisJcmV0ID0gZXZ0LT5o YW5kbGVyKGV2dC0+ZXZ0LCBldnQtPmhhbmRsZXJfYXJnLCByZWdzKTsKKwlpZiAocmV0KQorCQlw cl93YXJuKCJldmVudCAleCBoYW5kbGVyIGZhaWxlZCB3aXRoIGVycm9yICVkXG4iLCBldnQtPmV2 dCwKKwkJCXJldCk7Cit9CisKK3N0YXRpYyBib29sIHNzZV9ldmVudF9pc19nbG9iYWwodTMyIGV2 dCkKK3sKKwlyZXR1cm4gISEoZXZ0ICYgU0JJX1NTRV9FVkVOVF9HTE9CQUwpOworfQorCitzdGF0 aWMKK3N0cnVjdCBzc2VfZXZlbnQgKnNzZV9ldmVudF9nZXQodTMyIGV2dCkKK3sKKwlzdHJ1Y3Qg c3NlX2V2ZW50ICpzc2VfZXZ0ID0gTlVMTCwgKnRtcDsKKworCXNjb3BlZF9ndWFyZChzcGlubG9j aywgJmV2ZW50c19saXN0X2xvY2spIHsKKwkJbGlzdF9mb3JfZWFjaF9lbnRyeSh0bXAsICZldmVu dHMsIGxpc3QpIHsKKwkJCWlmICh0bXAtPmV2dCA9PSBldnQpIHsKKwkJCQlyZXR1cm4gc3NlX2V2 dDsKKwkJCX0KKwkJfQorCX0KKworCXJldHVybiBOVUxMOworfQorCitzdGF0aWMgcGh5c19hZGRy X3Qgc3NlX2V2ZW50X2dldF9waHlzKHN0cnVjdCBzc2VfcmVnaXN0ZXJlZF9ldmVudCAqcmVnX2V2 dCwKKwkJCQkgICAgICB2b2lkICphZGRyKQoreworCXBoeXNfYWRkcl90IHBoeXM7CisKKwlpZiAo c3NlX2V2ZW50X2lzX2dsb2JhbChyZWdfZXZ0LT5ldnQtPmV2dCkpCisJCXBoeXMgPSB2aXJ0X3Rv X3BoeXMoYWRkcik7CisJZWxzZQorCQlwaHlzID0gcGVyX2NwdV9wdHJfdG9fcGh5cyhhZGRyKTsK KworCXJldHVybiBwaHlzOworfQorCitzdGF0aWMgaW50IHNzZV9zYmlfZXZlbnRfZnVuYyhzdHJ1 Y3Qgc3NlX2V2ZW50ICpldmVudCwgdW5zaWduZWQgbG9uZyBmdW5jKQoreworCXN0cnVjdCBzYmly ZXQgcmV0OworCXUzMiBldnQgPSBldmVudC0+ZXZ0OworCisJcmV0ID0gc2JpX2VjYWxsKFNCSV9F WFRfU1NFLCBmdW5jLCBldnQsIDAsIDAsIDAsIDAsIDApOworCWlmIChyZXQuZXJyb3IpCisJCXBy X2RlYnVnKCJGYWlsZWQgdG8gZXhlY3V0ZSBmdW5jICVseCwgZXZlbnQgJXgsIGVycm9yICVsZFxu IiwKKwkJCSBmdW5jLCBldnQsIHJldC5lcnJvcik7CisKKwlyZXR1cm4gc2JpX2Vycl9tYXBfbGlu dXhfZXJybm8ocmV0LmVycm9yKTsKK30KKworc3RhdGljIGludCBzc2Vfc2JpX2Rpc2FibGVfZXZl bnQoc3RydWN0IHNzZV9ldmVudCAqZXZlbnQpCit7CisJcmV0dXJuIHNzZV9zYmlfZXZlbnRfZnVu YyhldmVudCwgU0JJX1NTRV9FVkVOVF9ESVNBQkxFKTsKK30KKworc3RhdGljIGludCBzc2Vfc2Jp X2VuYWJsZV9ldmVudChzdHJ1Y3Qgc3NlX2V2ZW50ICpldmVudCkKK3sKKwlyZXR1cm4gc3NlX3Ni aV9ldmVudF9mdW5jKGV2ZW50LCBTQklfU1NFX0VWRU5UX0VOQUJMRSk7Cit9CisKK3N0YXRpYyBp bnQgc3NlX2V2ZW50X2F0dHJfZ2V0X25vX2xvY2soc3RydWN0IHNzZV9yZWdpc3RlcmVkX2V2ZW50 ICpyZWdfZXZ0LAorCQkJCSAgICAgIHVuc2lnbmVkIGxvbmcgYXR0cl9pZCwgdW5zaWduZWQgbG9u ZyAqdmFsKQoreworCXN0cnVjdCBzYmlyZXQgc3JldDsKKwl1MzIgZXZ0ID0gcmVnX2V2dC0+ZXZ0 LT5ldnQ7CisJdW5zaWduZWQgbG9uZyBwaHlzOworCisJcGh5cyA9IHNzZV9ldmVudF9nZXRfcGh5 cyhyZWdfZXZ0LCAmcmVnX2V2dC0+YXR0cl9idWYpOworCisJc3JldCA9IHNiaV9lY2FsbChTQklf RVhUX1NTRSwgU0JJX1NTRV9FVkVOVF9BVFRSX1JFQUQsIGV2dCwKKwkJCQkgICAgIGF0dHJfaWQs IDEsIHBoeXMsIDAsIDApOworCWlmIChzcmV0LmVycm9yKSB7CisJCXByX2RlYnVnKCJGYWlsZWQg dG8gZ2V0IGV2ZW50ICV4IGF0dHIgJWx4LCBlcnJvciAlbGRcbiIsIGV2dCwKKwkJCSBhdHRyX2lk LCBzcmV0LmVycm9yKTsKKwkJcmV0dXJuIHNiaV9lcnJfbWFwX2xpbnV4X2Vycm5vKHNyZXQuZXJy b3IpOworCX0KKworCSp2YWwgPSByZWdfZXZ0LT5hdHRyX2J1ZjsKKworCXJldHVybiAwOworfQor CitzdGF0aWMgaW50IHNzZV9ldmVudF9hdHRyX3NldF9ub2xvY2soc3RydWN0IHNzZV9yZWdpc3Rl cmVkX2V2ZW50ICpyZWdfZXZ0LAorCQkJCSAgICAgdW5zaWduZWQgbG9uZyBhdHRyX2lkLCB1bnNp Z25lZCBsb25nIHZhbCkKK3sKKwlzdHJ1Y3Qgc2JpcmV0IHNyZXQ7CisJdTMyIGV2dCA9IHJlZ19l dnQtPmV2dC0+ZXZ0OworCXVuc2lnbmVkIGxvbmcgcGh5czsKKworCXJlZ19ldnQtPmF0dHJfYnVm ID0gdmFsOworCXBoeXMgPSBzc2VfZXZlbnRfZ2V0X3BoeXMocmVnX2V2dCwgJnJlZ19ldnQtPmF0 dHJfYnVmKTsKKworCXNyZXQgPSBzYmlfZWNhbGwoU0JJX0VYVF9TU0UsIFNCSV9TU0VfRVZFTlRf QVRUUl9XUklURSwgZXZ0LAorCQkJCSAgICAgYXR0cl9pZCwgMSwgcGh5cywgMCwgMCk7CisJaWYg KHNyZXQuZXJyb3IgJiYgc3JldC5lcnJvciAhPSBTQklfRVJSX0lOVkFMSURfU1RBVEUpIHsKKwkJ cHJfZGVidWcoIkZhaWxlZCB0byBzZXQgZXZlbnQgJXggYXR0ciAlbHgsIGVycm9yICVsZFxuIiwg ZXZ0LAorCQkJIGF0dHJfaWQsIHNyZXQuZXJyb3IpOworCQlyZXR1cm4gc2JpX2Vycl9tYXBfbGlu dXhfZXJybm8oc3JldC5lcnJvcik7CisJfQorCisJcmV0dXJuIDA7Cit9CisKK3N0YXRpYyBpbnQg c3NlX2V2ZW50X3NldF90YXJnZXRfY3B1X25vbG9jayhzdHJ1Y3Qgc3NlX2V2ZW50ICpldmVudCwK KwkJCQkJICAgdW5zaWduZWQgaW50IGNwdSkKK3sKKwl1bnNpZ25lZCBpbnQgaGFydF9pZCA9IGNw dWlkX3RvX2hhcnRpZF9tYXAoY3B1KTsKKwlzdHJ1Y3Qgc3NlX3JlZ2lzdGVyZWRfZXZlbnQgKnJl Z19ldnQgPSBldmVudC0+Z2xvYmFsOworCXUzMiBldnQgPSBldmVudC0+ZXZ0OworCWJvb2wgd2Fz X2VuYWJsZWQ7CisJaW50IHJldDsKKworCWlmICghc3NlX2V2ZW50X2lzX2dsb2JhbChldnQpKQor CQlyZXR1cm4gLUVJTlZBTDsKKworCXdhc19lbmFibGVkID0gZXZlbnQtPmlzX2VuYWJsZWQ7CisJ aWYgKHdhc19lbmFibGVkKQorCQlzc2Vfc2JpX2Rpc2FibGVfZXZlbnQoZXZlbnQpOworCWRvIHsK KwkJcmV0ID0gc3NlX2V2ZW50X2F0dHJfc2V0X25vbG9jayhyZWdfZXZ0LAorCQkJCQkJU0JJX1NT RV9BVFRSX1BSRUZFUlJFRF9IQVJULAorCQkJCQkJaGFydF9pZCk7CisJfSB3aGlsZSAocmV0ID09 IC1FSU5WQUwpOworCisJaWYgKHJldCA9PSAwKQorCQlldmVudC0+Y3B1ID0gY3B1OworCisJaWYg KHdhc19lbmFibGVkKQorCQlzc2Vfc2JpX2VuYWJsZV9ldmVudChldmVudCk7CisKKwlyZXR1cm4g MDsKK30KKworaW50IHNzZV9ldmVudF9zZXRfdGFyZ2V0X2NwdShzdHJ1Y3Qgc3NlX2V2ZW50ICpl dmVudCwgdW5zaWduZWQgaW50IGNwdSkKK3sKKwlpbnQgcmV0OworCisJc2NvcGVkX2d1YXJkKG11 dGV4LCAmc3NlX211dGV4KSB7CisJCWNwdXNfcmVhZF9sb2NrKCk7CisKKwkJaWYgKCFjcHVfb25s aW5lKGNwdSkpCisJCQlyZXR1cm4gLUVJTlZBTDsKKworCQlyZXQgPSBzc2VfZXZlbnRfc2V0X3Rh cmdldF9jcHVfbm9sb2NrKGV2ZW50LCBjcHUpOworCisJCWNwdXNfcmVhZF91bmxvY2soKTsKKwl9 CisKKwlyZXR1cm4gcmV0OworfQorCitzdGF0aWMgaW50IHNzZV9ldmVudF9pbml0X3JlZ2lzdGVy ZWQodW5zaWduZWQgaW50IGNwdSwKKwkJCQkgICAgIHN0cnVjdCBzc2VfcmVnaXN0ZXJlZF9ldmVu dCAqcmVnX2V2dCwKKwkJCQkgICAgIHN0cnVjdCBzc2VfZXZlbnQgKmV2ZW50KQoreworCXJlZ19l dnQtPmV2dCA9IGV2ZW50OworCWFyY2hfc3NlX2luaXRfZXZlbnQoJnJlZ19ldnQtPmFyY2gsIGV2 ZW50LT5ldnQsIGNwdSk7CisKKwlyZXR1cm4gMDsKK30KKworc3RhdGljIHZvaWQgc3NlX2V2ZW50 X2ZyZWVfcmVnaXN0ZXJlZChzdHJ1Y3Qgc3NlX3JlZ2lzdGVyZWRfZXZlbnQgKnJlZ19ldnQpCit7 CisJYXJjaF9zc2VfZnJlZV9ldmVudCgmcmVnX2V2dC0+YXJjaCk7Cit9CisKK3N0YXRpYyBpbnQg c3NlX2V2ZW50X2FsbG9jX2dsb2JhbChzdHJ1Y3Qgc3NlX2V2ZW50ICpldmVudCkKK3sKKwlpbnQg ZXJyOworCXN0cnVjdCBzc2VfcmVnaXN0ZXJlZF9ldmVudCAqcmVnX2V2dDsKKworCXJlZ19ldnQg PSBremFsbG9jKHNpemVvZigqcmVnX2V2dCksIEdGUF9LRVJORUwpOworCWlmICghcmVnX2V2dCkK KwkJcmV0dXJuIC1FTk9NRU07CisKKwlldmVudC0+Z2xvYmFsID0gcmVnX2V2dDsKKwllcnIgPSBz c2VfZXZlbnRfaW5pdF9yZWdpc3RlcmVkKHNtcF9wcm9jZXNzb3JfaWQoKSwgcmVnX2V2dCwKKwkJ CQkJZXZlbnQpOworCWlmIChlcnIpCisJCWtmcmVlKHJlZ19ldnQpOworCisJcmV0dXJuIGVycjsK K30KKworc3RhdGljIGludCBzc2VfZXZlbnRfYWxsb2NfbG9jYWwoc3RydWN0IHNzZV9ldmVudCAq ZXZlbnQpCit7CisJaW50IGVycjsKKwl1bnNpZ25lZCBpbnQgY3B1LCBlcnJfY3B1OworCXN0cnVj dCBzc2VfcmVnaXN0ZXJlZF9ldmVudCAqcmVnX2V2dDsKKwlzdHJ1Y3Qgc3NlX3JlZ2lzdGVyZWRf ZXZlbnQgX19wZXJjcHUgKnJlZ19ldnRzOworCisJcmVnX2V2dHMgPSBhbGxvY19wZXJjcHUoc3Ry dWN0IHNzZV9yZWdpc3RlcmVkX2V2ZW50KTsKKwlpZiAoIXJlZ19ldnRzKQorCQlyZXR1cm4gLUVO T01FTTsKKworCWV2ZW50LT5sb2NhbCA9IHJlZ19ldnRzOworCisJZm9yX2VhY2hfcG9zc2libGVf Y3B1KGNwdSkgeworCQlyZWdfZXZ0ID0gcGVyX2NwdV9wdHIocmVnX2V2dHMsIGNwdSk7CisJCWVy ciA9IHNzZV9ldmVudF9pbml0X3JlZ2lzdGVyZWQoY3B1LCByZWdfZXZ0LCBldmVudCk7CisJCWlm IChlcnIpIHsKKwkJCWVycl9jcHUgPSBjcHU7CisJCQlnb3RvIGVycl9mcmVlX3Blcl9jcHU7CisJ CX0KKwl9CisKKwlyZXR1cm4gMDsKKworZXJyX2ZyZWVfcGVyX2NwdToKKwlmb3JfZWFjaF9wb3Nz aWJsZV9jcHUoY3B1KSB7CisJCWlmIChjcHUgPT0gZXJyX2NwdSkKKwkJCWJyZWFrOworCQlyZWdf ZXZ0ID0gcGVyX2NwdV9wdHIocmVnX2V2dHMsIGNwdSk7CisJCXNzZV9ldmVudF9mcmVlX3JlZ2lz dGVyZWQocmVnX2V2dCk7CisJfQorCisJZnJlZV9wZXJjcHUocmVnX2V2dHMpOworCisJcmV0dXJu IGVycjsKK30KKworc3RhdGljIHN0cnVjdCBzc2VfZXZlbnQgKnNzZV9ldmVudF9hbGxvYyh1MzIg ZXZ0LAorCQkJCQkgdTMyIHByaW9yaXR5LAorCQkJCQkgc3NlX2V2ZW50X2hhbmRsZXIgKmhhbmRs ZXIsIHZvaWQgKmFyZykKK3sKKwlpbnQgZXJyOworCXN0cnVjdCBzc2VfZXZlbnQgKmV2ZW50Owor CisJZXZlbnQgPSBremFsbG9jKHNpemVvZigqZXZlbnQpLCBHRlBfS0VSTkVMKTsKKwlpZiAoIWV2 ZW50KQorCQlyZXR1cm4gRVJSX1BUUigtRU5PTUVNKTsKKworCWV2ZW50LT5ldnQgPSBldnQ7CisJ ZXZlbnQtPnByaW9yaXR5ID0gcHJpb3JpdHk7CisJZXZlbnQtPmhhbmRsZXJfYXJnID0gYXJnOwor CWV2ZW50LT5oYW5kbGVyID0gaGFuZGxlcjsKKworCWlmIChzc2VfZXZlbnRfaXNfZ2xvYmFsKGV2 dCkpIHsKKwkJZXJyID0gc3NlX2V2ZW50X2FsbG9jX2dsb2JhbChldmVudCk7CisJCWlmIChlcnIp CisJCQlnb3RvIGVycl9hbGxvY19yZWdfZXZ0OworCX0gZWxzZSB7CisJCWVyciA9IHNzZV9ldmVu dF9hbGxvY19sb2NhbChldmVudCk7CisJCWlmIChlcnIpCisJCQlnb3RvIGVycl9hbGxvY19yZWdf ZXZ0OworCX0KKworCXJldHVybiBldmVudDsKKworZXJyX2FsbG9jX3JlZ19ldnQ6CisJa2ZyZWUo ZXZlbnQpOworCisJcmV0dXJuIEVSUl9QVFIoZXJyKTsKK30KKworc3RhdGljIGludCBzc2Vfc2Jp X3JlZ2lzdGVyX2V2ZW50KHN0cnVjdCBzc2VfZXZlbnQgKmV2ZW50LAorCQkJCSAgc3RydWN0IHNz ZV9yZWdpc3RlcmVkX2V2ZW50ICpyZWdfZXZ0KQoreworCWludCByZXQ7CisKKwlyZXQgPSBzc2Vf ZXZlbnRfYXR0cl9zZXRfbm9sb2NrKHJlZ19ldnQsIFNCSV9TU0VfQVRUUl9QUklPLAorCQkJCQll dmVudC0+cHJpb3JpdHkpOworCWlmIChyZXQpCisJCXJldHVybiByZXQ7CisKKwlyZXR1cm4gYXJj aF9zc2VfcmVnaXN0ZXJfZXZlbnQoJnJlZ19ldnQtPmFyY2gpOworfQorCitzdGF0aWMgaW50IHNz ZV9ldmVudF9yZWdpc3Rlcl9sb2NhbChzdHJ1Y3Qgc3NlX2V2ZW50ICpldmVudCkKK3sKKwlpbnQg cmV0OworCXN0cnVjdCBzc2VfcmVnaXN0ZXJlZF9ldmVudCAqcmVnX2V2dCA9IHBlcl9jcHVfcHRy KGV2ZW50LT5sb2NhbCwKKwkJCQkJCQkgICBzbXBfcHJvY2Vzc29yX2lkKCkpOworCisJcmV0ID0g c3NlX3NiaV9yZWdpc3Rlcl9ldmVudChldmVudCwgcmVnX2V2dCk7CisJaWYgKHJldCkKKwkJcHJf ZGVidWcoIkZhaWxlZCB0byByZWdpc3RlciBldmVudCAleDogZXJyICVkXG4iLCBldmVudC0+ZXZ0 LAorCQkJIHJldCk7CisKKwlyZXR1cm4gcmV0OworfQorCisKK3N0YXRpYyBpbnQgc3NlX3NiaV91 bnJlZ2lzdGVyX2V2ZW50KHN0cnVjdCBzc2VfZXZlbnQgKmV2ZW50KQoreworCXJldHVybiBzc2Vf c2JpX2V2ZW50X2Z1bmMoZXZlbnQsIFNCSV9TU0VfRVZFTlRfVU5SRUdJU1RFUik7Cit9CisKK3N0 cnVjdCBzc2VfcGVyX2NwdV9ldnQgeworCXN0cnVjdCBzc2VfZXZlbnQgKmV2ZW50OworCXVuc2ln bmVkIGxvbmcgZnVuYzsKKwlhdG9taWNfdCBlcnJvcjsKK307CisKK3N0YXRpYyB2b2lkIHNzZV9l dmVudF9wZXJfY3B1X2Z1bmModm9pZCAqaW5mbykKK3sKKwlpbnQgcmV0OworCXN0cnVjdCBzc2Vf cGVyX2NwdV9ldnQgKmNwdV9ldnQgPSBpbmZvOworCisJaWYgKGNwdV9ldnQtPmZ1bmMgPT0gU0JJ X1NTRV9FVkVOVF9SRUdJU1RFUikKKwkJcmV0ID0gc3NlX2V2ZW50X3JlZ2lzdGVyX2xvY2FsKGNw dV9ldnQtPmV2ZW50KTsKKwllbHNlCisJCXJldCA9IHNzZV9zYmlfZXZlbnRfZnVuYyhjcHVfZXZ0 LT5ldmVudCwgY3B1X2V2dC0+ZnVuYyk7CisKKwlpZiAocmV0KQorCQlhdG9taWNfc2V0KCZjcHVf ZXZ0LT5lcnJvciwgcmV0KTsKK30KKworc3RhdGljIHZvaWQgc3NlX2V2ZW50X2ZyZWUoc3RydWN0 IHNzZV9ldmVudCAqZXZlbnQpCit7CisJdW5zaWduZWQgaW50IGNwdTsKKwlzdHJ1Y3Qgc3NlX3Jl Z2lzdGVyZWRfZXZlbnQgKnJlZ19ldnQ7CisKKwlpZiAoc3NlX2V2ZW50X2lzX2dsb2JhbChldmVu dC0+ZXZ0KSkgeworCQlzc2VfZXZlbnRfZnJlZV9yZWdpc3RlcmVkKGV2ZW50LT5nbG9iYWwpOwor CQlrZnJlZShldmVudC0+Z2xvYmFsKTsKKwl9IGVsc2UgeworCQlmb3JfZWFjaF9wb3NzaWJsZV9j cHUoY3B1KSB7CisJCQlyZWdfZXZ0ID0gcGVyX2NwdV9wdHIoZXZlbnQtPmxvY2FsLCBjcHUpOwor CQkJc3NlX2V2ZW50X2ZyZWVfcmVnaXN0ZXJlZChyZWdfZXZ0KTsKKwkJfQorCQlmcmVlX3BlcmNw dShldmVudC0+bG9jYWwpOworCX0KKworCWtmcmVlKGV2ZW50KTsKK30KKworaW50IHNzZV9ldmVu dF9lbmFibGUoc3RydWN0IHNzZV9ldmVudCAqZXZlbnQpCit7CisJaW50IHJldCA9IDA7CisJc3Ry dWN0IHNzZV9wZXJfY3B1X2V2dCBjcHVfZXZ0OworCisJc2NvcGVkX2d1YXJkKG11dGV4LCAmc3Nl X211dGV4KSB7CisJCWNwdXNfcmVhZF9sb2NrKCk7CisJCWlmIChzc2VfZXZlbnRfaXNfZ2xvYmFs KGV2ZW50LT5ldnQpKSB7CisJCQlyZXQgPSBzc2Vfc2JpX2VuYWJsZV9ldmVudChldmVudCk7CisJ CX0gZWxzZSB7CisJCQljcHVfZXZ0LmV2ZW50ID0gZXZlbnQ7CisJCQlhdG9taWNfc2V0KCZjcHVf ZXZ0LmVycm9yLCAwKTsKKwkJCWNwdV9ldnQuZnVuYyA9IFNCSV9TU0VfRVZFTlRfRU5BQkxFOwor CQkJb25fZWFjaF9jcHUoc3NlX2V2ZW50X3Blcl9jcHVfZnVuYywgJmNwdV9ldnQsIDEpOworCQkJ cmV0ID0gYXRvbWljX3JlYWQoJmNwdV9ldnQuZXJyb3IpOworCQkJaWYgKHJldCkgeworCQkJCWNw dV9ldnQuZnVuYyA9IFNCSV9TU0VfRVZFTlRfRElTQUJMRTsKKwkJCQlvbl9lYWNoX2NwdShzc2Vf ZXZlbnRfcGVyX2NwdV9mdW5jLCAmY3B1X2V2dCwKKwkJCQkJICAgIDEpOworCQkJfQorCQl9CisJ CWNwdXNfcmVhZF91bmxvY2soKTsKKworCQlpZiAocmV0ID09IDApCisJCQlldmVudC0+aXNfZW5h YmxlZCA9IHRydWU7CisJfQorCisJcmV0dXJuIHJldDsKK30KKworc3RhdGljIHZvaWQgc3NlX2V2 ZW50c19tYXNrKHZvaWQpCit7CisJc2JpX2VjYWxsKFNCSV9FWFRfU1NFLCBTQklfU1NFX0VWRU5U X0hBUlRfTUFTSywgMCwgMCwgMCwgMCwgMCwgMCk7Cit9CisKK3N0YXRpYyB2b2lkIHNzZV9ldmVu dHNfdW5tYXNrKHZvaWQpCit7CisJc2JpX2VjYWxsKFNCSV9FWFRfU1NFLCBTQklfU1NFX0VWRU5U X0hBUlRfVU5NQVNLLCAwLCAwLCAwLCAwLCAwLCAwKTsKK30KKworc3RhdGljIHZvaWQgc3NlX2V2 ZW50X2Rpc2FibGVfbm9sb2NrKHN0cnVjdCBzc2VfZXZlbnQgKmV2ZW50KQoreworCXN0cnVjdCBz c2VfcGVyX2NwdV9ldnQgY3B1X2V2dDsKKworCWlmIChzc2VfZXZlbnRfaXNfZ2xvYmFsKGV2ZW50 LT5ldnQpKSB7CisJCXNzZV9zYmlfZGlzYWJsZV9ldmVudChldmVudCk7CisJfSBlbHNlIHsKKwkJ Y3B1X2V2dC5ldmVudCA9IGV2ZW50OworCQljcHVfZXZ0LmZ1bmMgPSBTQklfU1NFX0VWRU5UX0RJ U0FCTEU7CisJCW9uX2VhY2hfY3B1KHNzZV9ldmVudF9wZXJfY3B1X2Z1bmMsICZjcHVfZXZ0LCAx KTsKKwl9Cit9CisKK3ZvaWQgc3NlX2V2ZW50X2Rpc2FibGUoc3RydWN0IHNzZV9ldmVudCAqZXZl bnQpCit7CisJc2NvcGVkX2d1YXJkKG11dGV4LCAmc3NlX211dGV4KSB7CisJCWNwdXNfcmVhZF9s b2NrKCk7CisJCXNzZV9ldmVudF9kaXNhYmxlX25vbG9jayhldmVudCk7CisJCWV2ZW50LT5pc19l bmFibGVkID0gZmFsc2U7CisJCWNwdXNfcmVhZF91bmxvY2soKTsKKwl9Cit9CisKK3N0cnVjdCBz c2VfZXZlbnQgKnNzZV9ldmVudF9yZWdpc3Rlcih1MzIgZXZ0LCB1MzIgcHJpb3JpdHksCisJCQkJ ICAgICBzc2VfZXZlbnRfaGFuZGxlciAqaGFuZGxlciwgdm9pZCAqYXJnKQoreworCXN0cnVjdCBz c2VfcGVyX2NwdV9ldnQgY3B1X2V2dDsKKwlzdHJ1Y3Qgc3NlX2V2ZW50ICpldmVudDsKKwlpbnQg cmV0ID0gMDsKKworCWlmICghc3NlX2F2YWlsYWJsZSkKKwkJcmV0dXJuIEVSUl9QVFIoLUVPUE5P VFNVUFApOworCisJbXV0ZXhfbG9jaygmc3NlX211dGV4KTsKKwlpZiAoc3NlX2V2ZW50X2dldChl dnQpKSB7CisJCXByX2RlYnVnKCJFdmVudCAleCBhbHJlYWR5IHJlZ2lzdGVyZWRcbiIsIGV2dCk7 CisJCXJldCA9IC1FRVhJU1Q7CisJCWdvdG8gb3V0X3VubG9jazsKKwl9CisKKwlldmVudCA9IHNz ZV9ldmVudF9hbGxvYyhldnQsIHByaW9yaXR5LCBoYW5kbGVyLCBhcmcpOworCWlmIChJU19FUlIo ZXZlbnQpKSB7CisJCXJldCA9IFBUUl9FUlIoZXZlbnQpOworCQlnb3RvIG91dF91bmxvY2s7CisJ fQorCisJY3B1c19yZWFkX2xvY2soKTsKKwlpZiAoc3NlX2V2ZW50X2lzX2dsb2JhbChldnQpKSB7 CisJCXVuc2lnbmVkIGxvbmcgcHJlZmVycmVkX2hhcnQ7CisKKwkJcmV0ID0gc3NlX2V2ZW50X2F0 dHJfZ2V0X25vX2xvY2soZXZlbnQtPmdsb2JhbCwKKwkJCQkJCSBTQklfU1NFX0FUVFJfUFJFRkVS UkVEX0hBUlQsCisJCQkJCQkgJnByZWZlcnJlZF9oYXJ0KTsKKwkJaWYgKHJldCkKKwkJCWdvdG8g ZXJyX2V2ZW50X2ZyZWU7CisJCWV2ZW50LT5jcHUgPSByaXNjdl9oYXJ0aWRfdG9fY3B1aWQocHJl ZmVycmVkX2hhcnQpOworCisJCXJldCA9IHNzZV9zYmlfcmVnaXN0ZXJfZXZlbnQoZXZlbnQsIGV2 ZW50LT5nbG9iYWwpOworCQlpZiAocmV0KQorCQkJZ290byBlcnJfZXZlbnRfZnJlZTsKKworCX0g ZWxzZSB7CisJCWNwdV9ldnQuZXZlbnQgPSBldmVudDsKKwkJYXRvbWljX3NldCgmY3B1X2V2dC5l cnJvciwgMCk7CisJCWNwdV9ldnQuZnVuYyA9IFNCSV9TU0VfRVZFTlRfUkVHSVNURVI7CisJCW9u X2VhY2hfY3B1KHNzZV9ldmVudF9wZXJfY3B1X2Z1bmMsICZjcHVfZXZ0LCAxKTsKKwkJcmV0ID0g YXRvbWljX3JlYWQoJmNwdV9ldnQuZXJyb3IpOworCQlpZiAocmV0KSB7CisJCQljcHVfZXZ0LmZ1 bmMgPSBTQklfU1NFX0VWRU5UX1VOUkVHSVNURVI7CisJCQlvbl9lYWNoX2NwdShzc2VfZXZlbnRf cGVyX2NwdV9mdW5jLCAmY3B1X2V2dCwgMSk7CisJCQlnb3RvIGVycl9ldmVudF9mcmVlOworCQl9 CisJfQorCWNwdXNfcmVhZF91bmxvY2soKTsKKworCXNjb3BlZF9ndWFyZChzcGlubG9jaywgJmV2 ZW50c19saXN0X2xvY2spCisJCWxpc3RfYWRkKCZldmVudC0+bGlzdCwgJmV2ZW50cyk7CisKKwlt dXRleF91bmxvY2soJnNzZV9tdXRleCk7CisKKwlyZXR1cm4gZXZlbnQ7CisKK2Vycl9ldmVudF9m cmVlOgorCWNwdXNfcmVhZF91bmxvY2soKTsKKwlzc2VfZXZlbnRfZnJlZShldmVudCk7CitvdXRf dW5sb2NrOgorCW11dGV4X3VubG9jaygmc3NlX211dGV4KTsKKworCXJldHVybiBFUlJfUFRSKHJl dCk7Cit9CisKK3N0YXRpYyB2b2lkIHNzZV9ldmVudF91bnJlZ2lzdGVyX25vbG9jayhzdHJ1Y3Qg c3NlX2V2ZW50ICpldmVudCkKK3sKKwlzdHJ1Y3Qgc3NlX3Blcl9jcHVfZXZ0IGNwdV9ldnQ7CisK KwlpZiAoc3NlX2V2ZW50X2lzX2dsb2JhbChldmVudC0+ZXZ0KSkgeworCQlzc2Vfc2JpX3VucmVn aXN0ZXJfZXZlbnQoZXZlbnQpOworCX0gZWxzZSB7CisJCWNwdV9ldnQuZXZlbnQgPSBldmVudDsK KwkJY3B1X2V2dC5mdW5jID0gU0JJX1NTRV9FVkVOVF9VTlJFR0lTVEVSOworCQlvbl9lYWNoX2Nw dShzc2VfZXZlbnRfcGVyX2NwdV9mdW5jLCAmY3B1X2V2dCwgMSk7CisJfQorfQorCit2b2lkIHNz ZV9ldmVudF91bnJlZ2lzdGVyKHN0cnVjdCBzc2VfZXZlbnQgKmV2ZW50KQoreworCXNjb3BlZF9n dWFyZChtdXRleCwgJnNzZV9tdXRleCkgeworCQljcHVzX3JlYWRfbG9jaygpOworCQlzc2VfZXZl bnRfdW5yZWdpc3Rlcl9ub2xvY2soZXZlbnQpOworCQljcHVzX3JlYWRfdW5sb2NrKCk7CisKKwkJ c2NvcGVkX2d1YXJkKHNwaW5sb2NrLCAmZXZlbnRzX2xpc3RfbG9jaykKKwkJCWxpc3RfZGVsKCZl dmVudC0+bGlzdCk7CisKKwkJc3NlX2V2ZW50X2ZyZWUoZXZlbnQpOworCX0KK30KKworc3RhdGlj IGludCBzc2VfY3B1X29ubGluZSh1bnNpZ25lZCBpbnQgY3B1KQoreworCXN0cnVjdCBzc2VfZXZl bnQgKnNzZV9ldnQ7CisKKwlzY29wZWRfZ3VhcmQoc3BpbmxvY2ssICZldmVudHNfbGlzdF9sb2Nr KSB7CisJCWxpc3RfZm9yX2VhY2hfZW50cnkoc3NlX2V2dCwgJmV2ZW50cywgbGlzdCkgeworCQkJ aWYgKHNzZV9ldmVudF9pc19nbG9iYWwoc3NlX2V2dC0+ZXZ0KSkKKwkJCQljb250aW51ZTsKKwor CQkJc3NlX2V2ZW50X3JlZ2lzdGVyX2xvY2FsKHNzZV9ldnQpOworCQkJaWYgKHNzZV9ldnQtPmlz X2VuYWJsZWQpCisJCQkJc3NlX3NiaV9lbmFibGVfZXZlbnQoc3NlX2V2dCk7CisJCX0KKwl9CisK KwkvKiBSZWFkeSB0byBoYW5kbGUgZXZlbnRzLiBVbm1hc2sgU1NFLiAqLworCXNzZV9ldmVudHNf dW5tYXNrKCk7CisKKwlyZXR1cm4gMDsKK30KKworc3RhdGljIGludCBzc2VfY3B1X3RlYXJkb3du KHVuc2lnbmVkIGludCBjcHUpCit7CisJdW5zaWduZWQgaW50IG5leHRfY3B1OworCXN0cnVjdCBz c2VfZXZlbnQgKnNzZV9ldnQ7CisKKwkvKiBNYXNrIHRoZSBzc2UgZXZlbnRzICovCisJc3NlX2V2 ZW50c19tYXNrKCk7CisKKwlzY29wZWRfZ3VhcmQoc3BpbmxvY2ssICZldmVudHNfbGlzdF9sb2Nr KSB7CisJCWxpc3RfZm9yX2VhY2hfZW50cnkoc3NlX2V2dCwgJmV2ZW50cywgbGlzdCkgeworCQkJ aWYgKCFzc2VfZXZlbnRfaXNfZ2xvYmFsKHNzZV9ldnQtPmV2dCkpIHsKKworCQkJCWlmIChzc2Vf ZXZ0LT5pc19lbmFibGVkKQorCQkJCQlzc2Vfc2JpX2Rpc2FibGVfZXZlbnQoc3NlX2V2dCk7CisK KwkJCQlzc2Vfc2JpX3VucmVnaXN0ZXJfZXZlbnQoc3NlX2V2dCk7CisJCQkJY29udGludWU7CisJ CQl9CisKKwkJCWlmIChzc2VfZXZ0LT5jcHUgIT0gc21wX3Byb2Nlc3Nvcl9pZCgpKQorCQkJCWNv bnRpbnVlOworCisJCQkvKiBVcGRhdGUgZGVzdGluYXRpb24gaGFydCBmb3IgZ2xvYmFsIGV2ZW50 ICovCisJCQluZXh0X2NwdSA9IGNwdW1hc2tfYW55X2J1dChjcHVfb25saW5lX21hc2ssIGNwdSk7 CisJCQlzc2VfZXZlbnRfc2V0X3RhcmdldF9jcHVfbm9sb2NrKHNzZV9ldnQsIG5leHRfY3B1KTsK KwkJfQorCX0KKworCXJldHVybiAwOworfQorCitzdGF0aWMgdm9pZCBzc2VfcmVzZXQodm9pZCkK K3sKKwlzdHJ1Y3Qgc3NlX2V2ZW50ICpldmVudCA9IE5VTEw7CisKKwlsaXN0X2Zvcl9lYWNoX2Vu dHJ5KGV2ZW50LCAmZXZlbnRzLCBsaXN0KSB7CisJCXNzZV9ldmVudF9kaXNhYmxlX25vbG9jayhl dmVudCk7CisJCXNzZV9ldmVudF91bnJlZ2lzdGVyX25vbG9jayhldmVudCk7CisJfQorfQorCitz dGF0aWMgaW50IHNzZV9wbV9ub3RpZmllcihzdHJ1Y3Qgbm90aWZpZXJfYmxvY2sgKm5iLCB1bnNp Z25lZCBsb25nIGFjdGlvbiwKKwkJCSAgIHZvaWQgKmRhdGEpCit7CisJV0FSTl9PTl9PTkNFKHBy ZWVtcHRpYmxlKCkpOworCisJc3dpdGNoIChhY3Rpb24pIHsKKwljYXNlIENQVV9QTV9FTlRFUjoK KwkJc3NlX2V2ZW50c19tYXNrKCk7CisJCWJyZWFrOworCWNhc2UgQ1BVX1BNX0VYSVQ6CisJY2Fz ZSBDUFVfUE1fRU5URVJfRkFJTEVEOgorCQlzc2VfZXZlbnRzX3VubWFzaygpOworCQlicmVhazsK KwlkZWZhdWx0OgorCQlyZXR1cm4gTk9USUZZX0RPTkU7CisJfQorCisJcmV0dXJuIE5PVElGWV9P SzsKK30KKworc3RhdGljIHN0cnVjdCBub3RpZmllcl9ibG9jayBzc2VfcG1fbmIgPSB7CisJLm5v dGlmaWVyX2NhbGwgPSBzc2VfcG1fbm90aWZpZXIsCit9OworCisvKgorICogTWFzayBhbGwgQ1BV cyBhbmQgdW5yZWdpc3RlciBhbGwgZXZlbnRzIG9uIHBhbmljLCByZWJvb3Qgb3Iga2V4ZWMuCisg Ki8KK3N0YXRpYyBpbnQgc3NlX3JlYm9vdF9ub3RpZmllcihzdHJ1Y3Qgbm90aWZpZXJfYmxvY2sg Km5iLCB1bnNpZ25lZCBsb25nIGFjdGlvbiwKKwkJCQl2b2lkICpkYXRhKQoreworCWNwdWhwX3Jl bW92ZV9zdGF0ZShzc2VfaHBfc3RhdGUpOworCisJc3NlX3Jlc2V0KCk7CisKKwlyZXR1cm4gTk9U SUZZX09LOworfQorCitzdGF0aWMgc3RydWN0IG5vdGlmaWVyX2Jsb2NrIHNzZV9yZWJvb3RfbmIg PSB7CisJLm5vdGlmaWVyX2NhbGwgPSBzc2VfcmVib290X25vdGlmaWVyLAorfTsKKworc3RhdGlj IGludCBfX2luaXQgc3NlX2luaXQodm9pZCkKK3sKKwlpbnQgY3B1LCByZXQ7CisKKwlpZiAoc2Jp X3Byb2JlX2V4dGVuc2lvbihTQklfRVhUX1NTRSkgPD0gMCkgeworCQlwcl9lcnIoIk1pc3Npbmcg U0JJIFNTRSBleHRlbnNpb25cbiIpOworCQlyZXR1cm4gLUVPUE5PVFNVUFA7CisJfQorCXByX2lu Zm8oIlNCSSBTU0UgZXh0ZW5zaW9uIGRldGVjdGVkXG4iKTsKKworCWZvcl9lYWNoX3Bvc3NpYmxl X2NwdShjcHUpCisJCUlOSVRfTElTVF9IRUFEKCZldmVudHMpOworCisJcmV0ID0gY3B1X3BtX3Jl Z2lzdGVyX25vdGlmaWVyKCZzc2VfcG1fbmIpOworCWlmIChyZXQpIHsKKwkJcHJfd2FybigiRmFp bGVkIHRvIHJlZ2lzdGVyIENQVSBQTSBub3RpZmllci4uLlxuIik7CisJCXJldHVybiByZXQ7CisJ fQorCisJcmV0ID0gcmVnaXN0ZXJfcmVib290X25vdGlmaWVyKCZzc2VfcmVib290X25iKTsKKwlp ZiAocmV0KSB7CisJCXByX3dhcm4oIkZhaWxlZCB0byByZWdpc3RlciByZWJvb3Qgbm90aWZpZXIu Li5cbiIpOworCQlnb3RvIHJlbW92ZV9jcHVwbTsKKwl9CisKKwlyZXQgPSBjcHVocF9zZXR1cF9z dGF0ZShDUFVIUF9BUF9PTkxJTkVfRFlOLCAicmlzY3Yvc3NlOm9ubGluZSIsCisJCQkJc3NlX2Nw dV9vbmxpbmUsIHNzZV9jcHVfdGVhcmRvd24pOworCWlmIChyZXQgPCAwKQorCQlnb3RvIHJlbW92 ZV9yZWJvb3Q7CisKKwlzc2VfaHBfc3RhdGUgPSByZXQ7CisJc3NlX2F2YWlsYWJsZSA9IHRydWU7 CisKKwlyZXR1cm4gMDsKKworcmVtb3ZlX3JlYm9vdDoKKwl1bnJlZ2lzdGVyX3JlYm9vdF9ub3Rp Zmllcigmc3NlX3JlYm9vdF9uYik7CisKK3JlbW92ZV9jcHVwbToKKwljcHVfcG1fdW5yZWdpc3Rl cl9ub3RpZmllcigmc3NlX3BtX25iKTsKKworCXJldHVybiByZXQ7Cit9CithcmNoX2luaXRjYWxs KHNzZV9pbml0KTsKZGlmZiAtLWdpdCBhL2luY2x1ZGUvbGludXgvcmlzY3Zfc3NlLmggYi9pbmNs dWRlL2xpbnV4L3Jpc2N2X3NzZS5oCm5ldyBmaWxlIG1vZGUgMTAwNjQ0CmluZGV4IDAwMDAwMDAw MDAwMC4uYzczMTg0MDc0YjhjCi0tLSAvZGV2L251bGwKKysrIGIvaW5jbHVkZS9saW51eC9yaXNj dl9zc2UuaApAQCAtMCwwICsxLDU2IEBACisvKiBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BM LTIuMCAqLworLyoKKyAqIENvcHlyaWdodCAoQykgMjAyNCBSaXZvcyBJbmMuCisgKi8KKworI2lm bmRlZiBfX0xJTlVYX1JJU0NWX1NTRV9ICisjZGVmaW5lIF9fTElOVVhfUklTQ1ZfU1NFX0gKKwor I2luY2x1ZGUgPGxpbnV4L3R5cGVzLmg+CisjaW5jbHVkZSA8bGludXgvbGlua2FnZS5oPgorCitz dHJ1Y3Qgc3NlX2V2ZW50Oworc3RydWN0IHB0X3JlZ3M7CisKK3R5cGVkZWYgaW50IChzc2VfZXZl bnRfaGFuZGxlcikodTMyIGV2ZW50X251bSwgdm9pZCAqYXJnLCBzdHJ1Y3QgcHRfcmVncyAqcmVn cyk7CisKKyNpZmRlZiBDT05GSUdfUklTQ1ZfU1NFCisKK3N0cnVjdCBzc2VfZXZlbnQgKnNzZV9l dmVudF9yZWdpc3Rlcih1MzIgZXZlbnRfbnVtLCB1MzIgcHJpb3JpdHksCisJCQkJICAgICBzc2Vf ZXZlbnRfaGFuZGxlciAqaGFuZGxlciwgdm9pZCAqYXJnKTsKKwordm9pZCBzc2VfZXZlbnRfdW5y ZWdpc3RlcihzdHJ1Y3Qgc3NlX2V2ZW50ICpldnQpOworCitpbnQgc3NlX2V2ZW50X3NldF90YXJn ZXRfY3B1KHN0cnVjdCBzc2VfZXZlbnQgKnNzZV9ldnQsIHVuc2lnbmVkIGludCBjcHUpOworCitp bnQgc3NlX2V2ZW50X2VuYWJsZShzdHJ1Y3Qgc3NlX2V2ZW50ICpzc2VfZXZ0KTsKKwordm9pZCBz c2VfZXZlbnRfZGlzYWJsZShzdHJ1Y3Qgc3NlX2V2ZW50ICpzc2VfZXZ0KTsKKworI2Vsc2UKK3N0 YXRpYyBpbmxpbmUgc3RydWN0IHNzZV9ldmVudCAqc3NlX2V2ZW50X3JlZ2lzdGVyKHUzMiBldmVu dF9udW0sIHUzMiBwcmlvcml0eSwKKwkJCQkJCSAgIHNzZV9ldmVudF9oYW5kbGVyICpoYW5kbGVy LAorCQkJCQkJICAgdm9pZCAqYXJnKQoreworCXJldHVybiBFUlJfUFRSKC1FT1BOT1RTVVBQKTsK K30KKworc3RhdGljIGlubGluZSB2b2lkIHNzZV9ldmVudF91bnJlZ2lzdGVyKHN0cnVjdCBzc2Vf ZXZlbnQgKmV2dCkge30KKworc3RhdGljIGlubGluZSBpbnQgc3NlX2V2ZW50X3NldF90YXJnZXRf Y3B1KHN0cnVjdCBzc2VfZXZlbnQgKnNzZV9ldnQsCisJCQkJCSAgIHVuc2lnbmVkIGludCBjcHUp Cit7CisJcmV0dXJuIC1FT1BOT1RTVVBQOworfQorCitzdGF0aWMgaW5saW5lIGludCBzc2VfZXZl bnRfZW5hYmxlKHN0cnVjdCBzc2VfZXZlbnQgKnNzZV9ldnQpCit7CisJcmV0dXJuIC1FT1BOT1RT VVBQOworfQorCitzdGF0aWMgaW5saW5lIHZvaWQgc3NlX2V2ZW50X2Rpc2FibGUoc3RydWN0IHNz ZV9ldmVudCAqc3NlX2V2dCkge30KKworCisjZW5kaWYKKworI2VuZGlmIC8qIF9fTElOVVhfUklT Q1ZfU1NFX0ggKi8KLS0gCjIuNDUuMgoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fCmxpbnV4LXJpc2N2IG1haWxpbmcgbGlzdApsaW51eC1yaXNjdkBsaXN0 cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGlu Zm8vbGludXgtcmlzY3YK