From: Eric Biggers <ebiggers@kernel.org>
To: linux-crypto@vger.kernel.org
Cc: x86@kernel.org
Subject: [PATCH 3/7] crypto: x86/aes-xts - use .irp when useful
Date: Tue, 10 Dec 2024 15:58:30 -0800 [thread overview]
Message-ID: <20241210235834.40862-4-ebiggers@kernel.org> (raw)
In-Reply-To: <20241210235834.40862-1-ebiggers@kernel.org>
From: Eric Biggers <ebiggers@google.com>
Use .irp instead of repeating code.
No change in the generated code.
Signed-off-by: Eric Biggers <ebiggers@google.com>
---
arch/x86/crypto/aes-xts-avx-x86_64.S | 50 +++++-----------------------
1 file changed, 9 insertions(+), 41 deletions(-)
diff --git a/arch/x86/crypto/aes-xts-avx-x86_64.S b/arch/x86/crypto/aes-xts-avx-x86_64.S
index 48f97b79f7a9c..63e5d3b3e77f5 100644
--- a/arch/x86/crypto/aes-xts-avx-x86_64.S
+++ b/arch/x86/crypto/aes-xts-avx-x86_64.S
@@ -110,43 +110,17 @@
.macro _define_aliases
// Define register aliases V0-V15, or V0-V31 if all 32 SIMD registers
// are available, that map to the xmm, ymm, or zmm registers according
// to the selected Vector Length (VL).
- _define_Vi 0
- _define_Vi 1
- _define_Vi 2
- _define_Vi 3
- _define_Vi 4
- _define_Vi 5
- _define_Vi 6
- _define_Vi 7
- _define_Vi 8
- _define_Vi 9
- _define_Vi 10
- _define_Vi 11
- _define_Vi 12
- _define_Vi 13
- _define_Vi 14
- _define_Vi 15
+.irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
+ _define_Vi \i
+.endr
.if USE_AVX10
- _define_Vi 16
- _define_Vi 17
- _define_Vi 18
- _define_Vi 19
- _define_Vi 20
- _define_Vi 21
- _define_Vi 22
- _define_Vi 23
- _define_Vi 24
- _define_Vi 25
- _define_Vi 26
- _define_Vi 27
- _define_Vi 28
- _define_Vi 29
- _define_Vi 30
- _define_Vi 31
+.irp i, 16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+ _define_Vi \i
+.endr
.endif
// V0-V3 hold the data blocks during the main loop, or temporary values
// otherwise. V4-V5 hold temporary values.
@@ -616,19 +590,13 @@
_vaes_4x \enc, 0, 2
.Laes192\@:
_vaes_4x \enc, 0, 3
_vaes_4x \enc, 0, 4
.Laes128\@:
- _vaes_4x \enc, 0, 5
- _vaes_4x \enc, 0, 6
- _vaes_4x \enc, 0, 7
- _vaes_4x \enc, 0, 8
- _vaes_4x \enc, 0, 9
- _vaes_4x \enc, 0, 10
- _vaes_4x \enc, 0, 11
- _vaes_4x \enc, 0, 12
- _vaes_4x \enc, 0, 13
+.irp i, 5,6,7,8,9,10,11,12,13
+ _vaes_4x \enc, 0, \i
+.endr
_vaes_4x \enc, 1, 14
// XOR in the tweaks again.
_vpxor TWEAK0, V0, V0
_vpxor TWEAK1, V1, V1
--
2.47.1
next prev parent reply other threads:[~2024-12-10 23:59 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-10 23:58 [PATCH 0/7] crypto: x86 - minor optimizations and cleanup to VAES code Eric Biggers
2024-12-10 23:58 ` [PATCH 1/7] crypto: x86/aes-gcm - code size optimization Eric Biggers
2024-12-10 23:58 ` [PATCH 2/7] crypto: x86/aes-gcm - tune better for AMD CPUs Eric Biggers
2024-12-10 23:58 ` Eric Biggers [this message]
2024-12-10 23:58 ` [PATCH 4/7] crypto: x86/aes-xts - make the register aliases per-function Eric Biggers
2024-12-10 23:58 ` [PATCH 5/7] crypto: x86/aes-xts - improve some comments Eric Biggers
2024-12-10 23:58 ` [PATCH 6/7] crypto: x86/aes-xts - change len parameter to int Eric Biggers
2024-12-10 23:58 ` [PATCH 7/7] crypto: x86/aes-xts - more code size optimizations Eric Biggers
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