From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org
Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
linux-perf-users@vger.kernel.org,
Josh Poimboeuf <jpoimboe@kernel.org>,
Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Ricardo Neri <ricardo.neri-calderon@linux.intel.com>,
"Liang, Kan" <kan.liang@linux.intel.com>,
Andrew Cooper <andrew.cooper3@citrix.com>,
Brice Goglin <brice.goglin@gmail.com>,
Mario Limonciello <mario.limonciello@amd.com>,
Perry Yuan <Perry.Yuan@amd.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>
Subject: [PATCH v5 8/9] x86/bugs: Declutter vulnerable CPU list
Date: Wed, 11 Dec 2024 22:58:03 -0800 [thread overview]
Message-ID: <20241211-add-cpu-type-v5-8-2ae010f50370@linux.intel.com> (raw)
In-Reply-To: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com>
The affected processor table has a lot of repetition and redundant
information that can be omitted for brevity. Like:
VULNBL_INTEL_STEPPINGS(INTEL_IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
can easily be simplified to:
VULNBL_INTEL(IVYBRIDGE, SRBDS),
Apply this to all the entries in the affected processor table.
No functional change.
Disassembly of cpu_vuln_blacklist:
objdump -j .init.data --disassemble=cpu_vuln_blacklist vmlinux
doesn't show any difference before and after the change.
Acked-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
---
arch/x86/kernel/cpu/common.c | 143 ++++++++++++++++++++++---------------------
1 file changed, 73 insertions(+), 70 deletions(-)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index a5c28975c608..6c45b8bed9fc 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1126,7 +1126,7 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
#define VULNWL_INTEL(vfm, whitelist) \
- X86_MATCH_VFM(vfm, whitelist)
+ X86_MATCH_VFM(INTEL_##vfm, whitelist)
#define VULNWL_AMD(family, whitelist) \
VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
@@ -1143,32 +1143,32 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION),
/* Intel Family 6 */
- VULNWL_INTEL(INTEL_TIGERLAKE, NO_MMIO),
- VULNWL_INTEL(INTEL_TIGERLAKE_L, NO_MMIO),
- VULNWL_INTEL(INTEL_ALDERLAKE, NO_MMIO),
- VULNWL_INTEL(INTEL_ALDERLAKE_L, NO_MMIO),
+ VULNWL_INTEL(TIGERLAKE, NO_MMIO),
+ VULNWL_INTEL(TIGERLAKE_L, NO_MMIO),
+ VULNWL_INTEL(ALDERLAKE, NO_MMIO),
+ VULNWL_INTEL(ALDERLAKE_L, NO_MMIO),
- VULNWL_INTEL(INTEL_ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
- VULNWL_INTEL(INTEL_ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
- VULNWL_INTEL(INTEL_ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
- VULNWL_INTEL(INTEL_ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
- VULNWL_INTEL(INTEL_ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
+ VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
+ VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
+ VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
+ VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
+ VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
- VULNWL_INTEL(INTEL_ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
- VULNWL_INTEL(INTEL_ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
- VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
- VULNWL_INTEL(INTEL_ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
- VULNWL_INTEL(INTEL_XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
- VULNWL_INTEL(INTEL_XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
+ VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
+ VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
+ VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
+ VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
+ VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
+ VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
- VULNWL_INTEL(INTEL_CORE_YONAH, NO_SSB),
+ VULNWL_INTEL(CORE_YONAH, NO_SSB),
- VULNWL_INTEL(INTEL_ATOM_AIRMONT_MID, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY),
- VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
+ VULNWL_INTEL(ATOM_AIRMONT_MID, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY),
+ VULNWL_INTEL(ATOM_AIRMONT_NP, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
- VULNWL_INTEL(INTEL_ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
- VULNWL_INTEL(INTEL_ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
- VULNWL_INTEL(INTEL_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
+ VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
+ VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
+ VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
/*
* Technically, swapgs isn't serializing on AMD (despite it previously
@@ -1178,9 +1178,9 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
* good enough for our purposes.
*/
- VULNWL_INTEL(INTEL_ATOM_TREMONT, NO_EIBRS_PBRSB),
- VULNWL_INTEL(INTEL_ATOM_TREMONT_L, NO_EIBRS_PBRSB),
- VULNWL_INTEL(INTEL_ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB),
+ VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB),
+ VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB),
+ VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB),
/* AMD Family 0xf - 0x12 */
VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI),
@@ -1201,8 +1201,11 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
#define VULNBL(vendor, family, model, blacklist) \
X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist)
-#define VULNBL_INTEL_STEPPINGS(vfm, steppings, issues) \
- X86_MATCH_VFM_STEPPINGS(vfm, steppings, issues)
+#define VULNBL_INTEL(vfm, issues) \
+ X86_MATCH_VFM(INTEL_##vfm, issues)
+
+#define VULNBL_INTEL_STEPPINGS(vfm, steppings, issues) \
+ X86_MATCH_VFM_STEPPINGS(INTEL_##vfm, steppings, issues)
#define VULNBL_AMD(family, blacklist) \
VULNBL(AMD, family, X86_MODEL_ANY, blacklist)
@@ -1227,49 +1230,49 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
#define RFDS BIT(7)
static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
- VULNBL_INTEL_STEPPINGS(INTEL_IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
- VULNBL_INTEL_STEPPINGS(INTEL_HASWELL, X86_STEPPING_ANY, SRBDS),
- VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_L, X86_STEPPING_ANY, SRBDS),
- VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_G, X86_STEPPING_ANY, SRBDS),
- VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_X, X86_STEPPING_ANY, MMIO),
- VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPING_ANY, MMIO),
- VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_G, X86_STEPPING_ANY, SRBDS),
- VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_X, X86_STEPPING_ANY, MMIO),
- VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL, X86_STEPPING_ANY, SRBDS),
- VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
- VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
- VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
- VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
- VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
- VULNBL_INTEL_STEPPINGS(INTEL_CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED),
- VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
- VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS),
- VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS),
- VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
- VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED),
- VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
- VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE_L, X86_STEPPING_ANY, GDS),
- VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE, X86_STEPPING_ANY, GDS),
- VULNBL_INTEL_STEPPINGS(INTEL_LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED),
- VULNBL_INTEL_STEPPINGS(INTEL_ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
- VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE, X86_STEPPING_ANY, RFDS),
- VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE_L, X86_STEPPING_ANY, RFDS),
- VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE, X86_STEPPING_ANY, RFDS),
- VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_P, X86_STEPPING_ANY, RFDS),
- VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_S, X86_STEPPING_ANY, RFDS),
- VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GRACEMONT, X86_STEPPING_ANY, RFDS),
- VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS),
- VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO | RFDS),
- VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS),
- VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT, X86_STEPPING_ANY, RFDS),
- VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_D, X86_STEPPING_ANY, RFDS),
- VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEPPING_ANY, RFDS),
-
- VULNBL_AMD(0x15, RETBLEED),
- VULNBL_AMD(0x16, RETBLEED),
- VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO),
- VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO),
- VULNBL_AMD(0x19, SRSO),
+ VULNBL_INTEL( IVYBRIDGE, SRBDS),
+ VULNBL_INTEL( HASWELL, SRBDS),
+ VULNBL_INTEL( HASWELL_L, SRBDS),
+ VULNBL_INTEL( HASWELL_G, SRBDS),
+ VULNBL_INTEL( HASWELL_X, MMIO),
+ VULNBL_INTEL( BROADWELL_D, MMIO),
+ VULNBL_INTEL( BROADWELL_G, SRBDS),
+ VULNBL_INTEL( BROADWELL_X, MMIO),
+ VULNBL_INTEL( BROADWELL, SRBDS),
+ VULNBL_INTEL( SKYLAKE_X, MMIO | RETBLEED | GDS),
+ VULNBL_INTEL( SKYLAKE_L, MMIO | RETBLEED | GDS | SRBDS),
+ VULNBL_INTEL( SKYLAKE, MMIO | RETBLEED | GDS | SRBDS),
+ VULNBL_INTEL( KABYLAKE_L, MMIO | RETBLEED | GDS | SRBDS),
+ VULNBL_INTEL( KABYLAKE, MMIO | RETBLEED | GDS | SRBDS),
+ VULNBL_INTEL( CANNONLAKE_L, RETBLEED),
+ VULNBL_INTEL( ICELAKE_L, MMIO | MMIO_SBDS | RETBLEED | GDS),
+ VULNBL_INTEL( ICELAKE_D, MMIO | GDS),
+ VULNBL_INTEL( ICELAKE_X, MMIO | GDS),
+ VULNBL_INTEL( COMETLAKE, MMIO | MMIO_SBDS | RETBLEED | GDS),
+ VULNBL_INTEL_STEPPINGS( COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED),
+ VULNBL_INTEL( COMETLAKE_L, MMIO | MMIO_SBDS | RETBLEED | GDS),
+ VULNBL_INTEL( TIGERLAKE_L, GDS),
+ VULNBL_INTEL( TIGERLAKE, GDS),
+ VULNBL_INTEL( LAKEFIELD, MMIO | MMIO_SBDS | RETBLEED),
+ VULNBL_INTEL( ROCKETLAKE, MMIO | RETBLEED | GDS),
+ VULNBL_INTEL( ALDERLAKE, RFDS),
+ VULNBL_INTEL( ALDERLAKE_L, RFDS),
+ VULNBL_INTEL( RAPTORLAKE, RFDS),
+ VULNBL_INTEL( RAPTORLAKE_P, RFDS),
+ VULNBL_INTEL( RAPTORLAKE_S, RFDS),
+ VULNBL_INTEL( ATOM_GRACEMONT, RFDS),
+ VULNBL_INTEL( ATOM_TREMONT, MMIO | MMIO_SBDS | RFDS),
+ VULNBL_INTEL( ATOM_TREMONT_D, MMIO | RFDS),
+ VULNBL_INTEL( ATOM_TREMONT_L, MMIO | MMIO_SBDS | RFDS),
+ VULNBL_INTEL( ATOM_GOLDMONT, RFDS),
+ VULNBL_INTEL( ATOM_GOLDMONT_D, RFDS),
+ VULNBL_INTEL( ATOM_GOLDMONT_PLUS, RFDS),
+
+ VULNBL_AMD( 0x15, RETBLEED),
+ VULNBL_AMD( 0x16, RETBLEED),
+ VULNBL_AMD( 0x17, RETBLEED | SMT_RSB | SRSO),
+ VULNBL_HYGON( 0x18, RETBLEED | SMT_RSB | SRSO),
+ VULNBL_AMD( 0x19, SRSO),
{}
};
--
2.34.1
next prev parent reply other threads:[~2024-12-12 6:58 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-12 6:57 [PATCH v5 0/9] Utilize cpu-type for CPU matching Pawan Gupta
2024-12-12 6:57 ` [PATCH v5 1/9] x86/cpu: Prepend 0x to the hex values in cpu_debug_show() Pawan Gupta
2025-02-27 12:55 ` [tip: x86/cpu] x86/cpu: Prefix hexadecimal values with 0x " tip-bot2 for Pawan Gupta
2024-12-12 6:57 ` [PATCH v5 2/9] cpufreq: intel_pstate: Avoid SMP calls to get cpu-type Pawan Gupta
2025-02-27 12:55 ` [tip: x86/cpu] " tip-bot2 for Pawan Gupta
2024-12-12 6:57 ` [PATCH v5 3/9] perf/x86/intel: Use cache cpu-type for hybrid PMU selection Pawan Gupta
2025-02-27 12:55 ` [tip: x86/cpu] " tip-bot2 for Pawan Gupta
2024-12-12 6:57 ` [PATCH v5 4/9] x86/cpu: Remove get_this_hybrid_cpu_*() Pawan Gupta
2025-02-27 12:55 ` [tip: x86/cpu] " tip-bot2 for Pawan Gupta
2024-12-12 6:57 ` [PATCH v5 5/9] x86/cpu: Name CPU matching macro more generically (and shorten) Pawan Gupta
2024-12-12 6:57 ` [PATCH v5 6/9] x86/cpu: Add cpu_type to struct x86_cpu_id Pawan Gupta
2024-12-12 6:57 ` [PATCH v5 7/9] x86/cpu: Update x86_match_cpu() to also use cpu-type Pawan Gupta
2024-12-12 6:58 ` Pawan Gupta [this message]
2024-12-12 6:58 ` [PATCH v5 9/9] x86/rfds: Exclude P-only parts from the RFDS affected list Pawan Gupta
2025-02-27 12:40 ` [PATCH v5 0/9] Utilize cpu-type for CPU matching Ingo Molnar
2025-02-27 17:51 ` Pawan Gupta
2025-02-27 18:28 ` Ingo Molnar
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