Re: [RFC PATCH v1] cxl: add support for cxl reset

[kernel test robot <lkp@intel.com>]

Hi Srirangan,

[This is a private test report for your RFC patch.]
kernel test robot noticed the following build warnings:

[auto build test WARNING on pci/next]
[also build test WARNING on pci/for-linus cxl/next linus/master v6.13-rc2 next-20241213]
[cannot apply to cxl/pending]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Srirangan-Madhavan/cxl-add-support-for-cxl-reset/20241213-154303
base:   https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link:    https://lore.kernel.org/r/20241213074143.374-1-smadhavan%40nvidia.com
patch subject: [RFC PATCH v1] cxl: add support for cxl reset
config: s390-randconfig-002-20241214 (https://download.01.org/0day-ci/archive/20241214/202412141749.12WRnc38-lkp@intel.com/config)
compiler: s390-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241214/202412141749.12WRnc38-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202412141749.12WRnc38-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/pci/pci.c:5197: warning: Function parameter or struct member 'dvsec' not described in 'cxl_reset_init'


vim +5197 drivers/pci/pci.c

  5189	
  5190	/**
  5191	 * cxl_reset_init - initiate a cxl reset
  5192	 * @dev: device to reset
  5193	 *
  5194	 * Initiate a cxl reset.
  5195	 */
  5196	static int cxl_reset_init(struct pci_dev *dev, u16 dvsec)
> 5197	{
  5198		u16 reg, val;
  5199		u32 timeout_ms;
  5200		int rc;
  5201		u32 reset_timeouts_ms[] = {10, 100, 1000, 10000, 100000};
  5202	
  5203		/*
  5204		 * Check if CXL Reset MEM CLR is supported.
  5205		 * TODO: Add check to do MEM CLR only if requested.
  5206		 */
  5207		rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCAP,
  5208					  &reg);
  5209		if (rc)
  5210			return rc;
  5211	
  5212		if (reg & PCI_DVSEC_CXL_DEVCAP_CXL_RST_MEM_CLR) {
  5213			rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2,
  5214						  &reg);
  5215			if (rc)
  5216				return rc;
  5217	
  5218			val = reg | PCI_DVSEC_CXL_DEVCTL2_CXL_RST_MEM_CLR_ENABLE;
  5219			pci_write_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2,
  5220					      val);
  5221		}
  5222	
  5223		/*
  5224		 * Read timeout value
  5225		 */
  5226		rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCAP,
  5227					  &reg);
  5228		if (rc)
  5229			return rc;
  5230		timeout_ms = reset_timeouts_ms[FIELD_GET(PCI_DVSEC_CXL_DEVCAP_CXL_RST_TIMEOUT_MASK, reg)];
  5231	
  5232		/*
  5233		 * Write reset config
  5234		 */
  5235		rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2,
  5236					  &reg);
  5237		if (rc)
  5238			return rc;
  5239	
  5240		val = reg | PCI_DVSEC_CXL_DEVCTL2_CXL_INIT_RST;
  5241		pci_write_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2,
  5242				      val);
  5243	
  5244		/*
  5245		 *  Wait till timeout and then check reset status is complete.
  5246		 */
  5247		msleep(timeout_ms);
  5248		rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVSTATUS2,
  5249					  &reg);
  5250		if (rc)
  5251			return rc;
  5252		if (reg & PCI_DVSEC_CXL_DEVSTATUS2_RST_ERR ||
  5253		    ~reg & PCI_DVSEC_CXL_DEVSTATUS2_RST_COMPLETE)
  5254			return -ETIMEDOUT;
  5255	
  5256		/*
  5257		 * Revert cashing disable.
  5258		 */
  5259		rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2,
  5260					  &reg);
  5261		if (rc)
  5262			return rc;
  5263		val = (reg & (~PCI_DVSEC_CXL_DEVCTL2_DISABLE_CACHING));
  5264		pci_write_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2,
  5265				      val);
  5266	
  5267		return 0;
  5268	}
  5269	

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