Re: [PATCH] FSL DDR: Errata A009942 clears board cpo_sample

[Peng Fan <peng.fan@oss.nxp.com>]

Joakim,

On Thu, Sep 19, 2024 at 04:00:16PM +0200, Joakim Tjernlund wrote:
>LSB in debug_28 register is cleared here so
>previous setting by errata A009942 is lost.
>Save and restore LSB in debug_28
>
>Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
>---
> drivers/ddr/fsl/fsl_ddr_gen4.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
>diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
>index 31c58d9a8e..1f8ff87a8b 100644
>--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
>+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
>@@ -477,6 +477,8 @@ step2:
> #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
> 	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
> 	val32 = ddr_in32(&ddr->debug[28]);
>+	temp32 = val32 & 0xff;
>+	debug("cpo_sample:%x\n", temp32);
> 	val32 &= 0xff0fff00;
> 	if (ddr_freq <= 1333)
> 		val32 |= 0x0080006a;
>@@ -487,6 +489,8 @@ step2:
> 	else if (ddr_freq <= 2133)
> 		val32 |= 0x0060007b;

The upper will set new value to lower 8bits.
But your code will make the 0x6a/0x7b be
restored.

I not understand well on the rational, would
you please give more details?

Thanks,
Peng

> 
>+	if (temp32)
>+		val32 = (val32 & ~0xff) | temp32;
> 	ddr_out32(&ddr->debug[28], val32);
> 	debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A009942\n");
> #endif
>-- 
>2.43.2
>
>