From: Rik van Riel <riel@surriel.com>
To: x86@kernel.org
Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com,
dave.hansen@linux.intel.com, luto@kernel.org,
peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com,
bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org,
linux-mm@kvack.org, Rik van Riel <riel@surriel.com>
Subject: [PATCH 02/11] x86/mm: add X86_FEATURE_INVLPGB definition.
Date: Sun, 22 Dec 2024 21:55:08 -0500 [thread overview]
Message-ID: <20241223025751.3268975-3-riel@surriel.com> (raw)
In-Reply-To: <20241223025751.3268975-1-riel@surriel.com>
Add the INVPLGB CPUID definition, allowing the kernel to recognize
whether the CPU supports the INVLPGB instruction.
Signed-off-by: Rik van Riel <riel@surriel.com>
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 17b6590748c0..b7209d6c3a5f 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -338,6 +338,7 @@
#define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */
#define X86_FEATURE_IRPERF (13*32+ 1) /* "irperf" Instructions Retired Count */
#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* "xsaveerptr" Always save/restore FP error pointers */
+#define X86_FEATURE_INVLPGB (13*32+ 3) /* "invlpgb" INVLPGB instruction */
#define X86_FEATURE_RDPRU (13*32+ 4) /* "rdpru" Read processor register at user level */
#define X86_FEATURE_WBNOINVD (13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */
#define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */
--
2.47.1
next prev parent reply other threads:[~2024-12-23 3:02 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-23 2:55 [RFC PATCH v2 00/11] AMD broadcast TLB invalidation Rik van Riel
2024-12-23 2:55 ` [PATCH 01/11] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Rik van Riel
2024-12-23 6:01 ` Qi Zheng
2024-12-23 20:20 ` Rik van Riel
2024-12-24 18:26 ` Peter Zijlstra
2024-12-23 2:55 ` Rik van Riel [this message]
2024-12-23 2:55 ` [PATCH 03/11] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2024-12-25 23:42 ` Nadav Amit
2024-12-23 2:55 ` [PATCH 04/11] x86/mm: add INVLPGB support code Rik van Riel
2024-12-23 2:55 ` [PATCH 05/11] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2024-12-23 2:55 ` [PATCH 06/11] x86/tlb: use INVLPGB in flush_tlb_all Rik van Riel
2024-12-23 2:55 ` [PATCH 07/11] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2024-12-23 2:55 ` [PATCH 08/11] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2024-12-25 23:22 ` Nadav Amit
2024-12-25 23:32 ` Nadav Amit
2024-12-23 2:55 ` [PATCH 09/11] x86,tlb: do targeted broadcast flushing from tlbbatch code Rik van Riel
2024-12-23 2:55 ` [PATCH 10/11] x86/mm: enable AMD translation cache extensions Rik van Riel
2024-12-23 2:55 ` [PATCH 11/11] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2024-12-24 18:08 ` [RFC PATCH v2 00/11] AMD broadcast TLB invalidation Michael Kelley
2024-12-25 14:48 ` Rik van Riel
2025-01-10 19:29 ` Tom Lendacky
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