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[209.51.188.17]) by mx.google.com with ESMTPS id ada2fe7eead31-4b2bfb739cfsi3089318137.496.2024.12.23.09.48.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Dec 2024 09:48:00 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nongnu.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tPmWr-00052J-QL; Mon, 23 Dec 2024 12:47:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tPmWq-00051x-2j; Mon, 23 Dec 2024 12:47:40 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tPmWn-0005Qw-Pr; Mon, 23 Dec 2024 12:47:39 -0500 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4YH56X1dT4z6LDSr; Tue, 24 Dec 2024 01:46:12 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 5AD64140517; Tue, 24 Dec 2024 01:47:24 +0800 (CST) Received: from localhost (10.47.75.118) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 23 Dec 2024 18:47:22 +0100 Date: Mon, 23 Dec 2024 17:47:20 +0000 To: Alireza Sanaee , CC: , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v4 2/7] target/arm/tcg: increase cache level for cpu=max Message-ID: <20241223174720.0000358e@huawei.com> In-Reply-To: <20241216175414.1953-3-alireza.sanaee@huawei.com> References: <20241216175414.1953-1-alireza.sanaee@huawei.com> <20241216175414.1953-3-alireza.sanaee@huawei.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.47.75.118] X-ClientProxiedBy: lhrpeml100009.china.huawei.com (7.191.174.83) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: jhsUsbQBQ+k6 On Mon, 16 Dec 2024 17:54:09 +0000 Alireza Sanaee wrote: > This patch addresses cache description in the `aarch64_max_tcg_initfn` > function for cpu=max. It introduces three layers of caches and modifies > the cache description registers accordingly. > > Signed-off-by: Alireza Sanaee I think this makes sense as a MAX cpu with out an L3 sounds pretty minimal and it provides a way to exercise the rest of this series in TCG. For KVM it will come from host registers (or overridden ones) anyway. Reviewed-by: Jonathan Cameron > --- > target/arm/tcg/cpu64.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c > index 904a7e90b4..47d8c9c9ae 100644 > --- a/target/arm/tcg/cpu64.c > +++ b/target/arm/tcg/cpu64.c > @@ -1086,6 +1086,19 @@ void aarch64_max_tcg_initfn(Object *obj) > uint64_t t; > uint32_t u; > > + /* > + * Expanded cache set > + */ > + cpu->clidr = 0x8200123; /* 4 4 3 in 3 bit fields */ > + /* 64KB L1 dcache */ > + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); > + /* 64KB L1 icache */ > + cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); > + /* 1MB L2 unified cache */ > + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7); > + /* 2MB L3 unified cache */ > + cpu->ccsidr[4] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 * MiB, 7); > + > /* > * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default > * to because we started with aarch64_a57_initfn(). A 'max' CPU might From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53FBDE7718B for ; Mon, 23 Dec 2024 17:48:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tPmWu-00053R-NX; Mon, 23 Dec 2024 12:47:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tPmWq-00051x-2j; Mon, 23 Dec 2024 12:47:40 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tPmWn-0005Qw-Pr; Mon, 23 Dec 2024 12:47:39 -0500 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4YH56X1dT4z6LDSr; Tue, 24 Dec 2024 01:46:12 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 5AD64140517; Tue, 24 Dec 2024 01:47:24 +0800 (CST) Received: from localhost (10.47.75.118) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 23 Dec 2024 18:47:22 +0100 Date: Mon, 23 Dec 2024 17:47:20 +0000 To: Alireza Sanaee , CC: , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v4 2/7] target/arm/tcg: increase cache level for cpu=max Message-ID: <20241223174720.0000358e@huawei.com> In-Reply-To: <20241216175414.1953-3-alireza.sanaee@huawei.com> References: <20241216175414.1953-1-alireza.sanaee@huawei.com> <20241216175414.1953-3-alireza.sanaee@huawei.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.47.75.118] X-ClientProxiedBy: lhrpeml100009.china.huawei.com (7.191.174.83) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, 16 Dec 2024 17:54:09 +0000 Alireza Sanaee wrote: > This patch addresses cache description in the `aarch64_max_tcg_initfn` > function for cpu=max. It introduces three layers of caches and modifies > the cache description registers accordingly. > > Signed-off-by: Alireza Sanaee I think this makes sense as a MAX cpu with out an L3 sounds pretty minimal and it provides a way to exercise the rest of this series in TCG. For KVM it will come from host registers (or overridden ones) anyway. Reviewed-by: Jonathan Cameron > --- > target/arm/tcg/cpu64.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c > index 904a7e90b4..47d8c9c9ae 100644 > --- a/target/arm/tcg/cpu64.c > +++ b/target/arm/tcg/cpu64.c > @@ -1086,6 +1086,19 @@ void aarch64_max_tcg_initfn(Object *obj) > uint64_t t; > uint32_t u; > > + /* > + * Expanded cache set > + */ > + cpu->clidr = 0x8200123; /* 4 4 3 in 3 bit fields */ > + /* 64KB L1 dcache */ > + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); > + /* 64KB L1 icache */ > + cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); > + /* 1MB L2 unified cache */ > + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7); > + /* 2MB L3 unified cache */ > + cpu->ccsidr[4] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 * MiB, 7); > + > /* > * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default > * to because we started with aarch64_a57_initfn(). A 'max' CPU might