From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: <alejandro.lucero-palau@amd.com>
Cc: <linux-cxl@vger.kernel.org>, <netdev@vger.kernel.org>,
<dan.j.williams@intel.com>, <martin.habets@xilinx.com>,
<edward.cree@amd.com>, <davem@davemloft.net>, <kuba@kernel.org>,
<pabeni@redhat.com>, <edumazet@google.com>,
<dave.jiang@intel.com>, Alejandro Lucero <alucerop@amd.com>
Subject: Re: [PATCH v8 17/27] cxl: define a driver interface for DPA allocation
Date: Tue, 24 Dec 2024 17:53:24 +0000 [thread overview]
Message-ID: <20241224175324.00001cad@huawei.com> (raw)
In-Reply-To: <20241216161042.42108-18-alejandro.lucero-palau@amd.com>
On Mon, 16 Dec 2024 16:10:32 +0000
<alejandro.lucero-palau@amd.com> wrote:
> From: Alejandro Lucero <alucerop@amd.com>
>
> Region creation involves finding available DPA (device-physical-address)
> capacity to map into HPA (host-physical-address) space. Given the HPA
> capacity constraint, define an API, cxl_request_dpa(), that has the
> flexibility to map the minimum amount of memory the driver needs to
Bonus space before map.
> operate vs the total possible that can be mapped given HPA availability.
>
> Factor out the core of cxl_dpa_alloc, that does free space scanning,
> into a cxl_dpa_freespace() helper, and use that to balance the capacity
> available to map vs the @min and @max arguments to cxl_request_dpa.
>
> Based on https://lore.kernel.org/linux-cxl/168592158743.1948938.7622563891193802610.stgit@dwillia2-xfh.jf.intel.com/
>
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> Co-developed-by: Dan Williams <dan.j.williams@intel.com>
Comments inline.
> ---
> drivers/cxl/core/hdm.c | 154 +++++++++++++++++++++++++++++++++++------
> include/cxl/cxl.h | 5 ++
> 2 files changed, 138 insertions(+), 21 deletions(-)
>
> +int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size)
> +{
> + struct cxl_port *port = cxled_to_port(cxled);
> + struct device *dev = &cxled->cxld.dev;
> + resource_size_t start, avail, skip;
> + int rc;
> +
> + down_write(&cxl_dpa_rwsem);
> + if (cxled->cxld.region) {
> + dev_dbg(dev, "EBUSY, decoder attached to %s\n",
> + dev_name(&cxled->cxld.region->dev));
> + rc = -EBUSY;
> + goto out;
> + }
> +
> + if (cxled->cxld.flags & CXL_DECODER_F_ENABLE) {
> + dev_dbg(dev, "EBUSY, decoder enabled\n");
> + rc = -EBUSY;
> goto out;
> }
>
> + avail = cxl_dpa_freespace(cxled, &start, &skip);
> +
> if (size > avail) {
> dev_dbg(dev, "%pa exceeds available %s capacity: %pa\n", &size,
> - cxl_decoder_mode_name(cxled->mode), &avail);
> + cxled->mode == CXL_DECODER_RAM ? "ram" : "pmem",
This is reverting an earlier change. I guess accidental?
> + &avail);
> rc = -ENOSPC;
> goto out;
> }
> @@ -538,6 +557,99 @@ int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size)
> return devm_add_action_or_reset(&port->dev, cxl_dpa_release, cxled);
> }
> +/**
> + * cxl_request_dpa - search and reserve DPA given input constraints
> + * @cxlmd: memdev with an endpoint port with available decoders
> + * @is_ram: DPA operation mode (ram vs pmem)
> + * @min: the minimum amount of capacity the call needs
> + * @max: extra capacity to allocate after min is satisfied
Includes the extra capacity. Otherwise capacity allocated as documented
is min + max which seems unlikely.
> + *
> + * Given that a region needs to allocate from limited HPA capacity it
> + * may be the case that a device has more mappable DPA capacity than
> + * available HPA. So, the expectation is that @min is a driver known
> + * value for how much capacity is needed, and @max is based the limit of
> + * how much HPA space is available for a new region.
> + *
> + * Returns a pinned cxl_decoder with at least @min bytes of capacity
> + * reserved, or an error pointer. The caller is also expected to own the
> + * lifetime of the memdev registration associated with the endpoint to
> + * pin the decoder registered as well.
> + */
> +struct cxl_endpoint_decoder *cxl_request_dpa(struct cxl_memdev *cxlmd,
> + bool is_ram,
> + resource_size_t min,
> + resource_size_t max)
> +{
> + struct cxl_port *endpoint = cxlmd->endpoint;
> + struct cxl_endpoint_decoder *cxled;
> + enum cxl_decoder_mode mode;
> + struct device *cxled_dev;
> + resource_size_t alloc;
> + int rc;
> +
> + if (!IS_ALIGNED(min | max, SZ_256M))
> + return ERR_PTR(-EINVAL);
> +
> + down_read(&cxl_dpa_rwsem);
> + cxled_dev = device_find_child(&endpoint->dev, NULL, find_free_decoder);
> + up_read(&cxl_dpa_rwsem);
> +
> + if (!cxled_dev)
> + cxled = ERR_PTR(-ENXIO);
if (!cxled_dev)
return ERR_PTR(-ENXIO);
cxled = to...
if (!cxled) //assuming this has any way to fail in which
case I think you would need to put the device...
put_device(cxled_dev);
return NULL;
Though do you actualy want to return an error in this case?
> + else
> + cxled = to_cxl_endpoint_decoder(cxled_dev);
> +
> + if (!cxled || IS_ERR(cxled))
> + return cxled;
Drop this with changes above.
> +
> + if (is_ram)
> + mode = CXL_DECODER_RAM;
> + else
> + mode = CXL_DECODER_PMEM;
> +
> + rc = cxl_dpa_set_mode(cxled, mode);
> + if (rc)
> + goto err;
> +
> + down_read(&cxl_dpa_rwsem);
> + alloc = cxl_dpa_freespace(cxled, NULL, NULL);
> + up_read(&cxl_dpa_rwsem);
> +
> + if (max)
> + alloc = min(max, alloc);
> + if (alloc < min) {
> + rc = -ENOMEM;
> + goto err;
> + }
> +
> + rc = cxl_dpa_alloc(cxled, alloc);
> + if (rc)
> + goto err;
> +
> + return cxled;
> +err:
> + put_device(cxled_dev);
> + return ERR_PTR(rc);
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_request_dpa, "CXL");
next prev parent reply other threads:[~2024-12-24 17:53 UTC|newest]
Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-16 16:10 [PATCH v8 00/27] cxl: add type2 device basic support alejandro.lucero-palau
2024-12-16 16:10 ` [PATCH v8 01/27] " alejandro.lucero-palau
2024-12-24 16:35 ` Jonathan Cameron
2024-12-27 6:56 ` Alejandro Lucero Palau
2025-01-07 16:35 ` Alison Schofield
2025-01-07 23:42 ` Dan Williams
2025-01-08 1:33 ` Dan Williams
2025-01-08 14:32 ` Alejandro Lucero Palau
2025-01-14 14:35 ` Alejandro Lucero Palau
2025-01-14 16:40 ` Alejandro Lucero Palau
2025-01-14 22:52 ` Dan Williams
2025-01-15 16:01 ` Alejandro Lucero Palau
2025-01-16 6:16 ` Dan Williams
2025-01-16 10:02 ` Alejandro Lucero Palau
2025-02-05 20:05 ` Dan Williams
2025-02-06 17:37 ` Alejandro Lucero Palau
2025-02-07 1:57 ` Dan Williams
2025-01-24 13:38 ` Alejandro Lucero Palau
2025-01-08 14:11 ` Alejandro Lucero Palau
2025-01-14 23:48 ` Dan Williams
2024-12-16 16:10 ` [PATCH v8 02/27] sfc: add cxl support using new CXL API alejandro.lucero-palau
2024-12-24 17:04 ` Jonathan Cameron
2024-12-27 7:00 ` Alejandro Lucero Palau
2025-01-08 1:56 ` Dan Williams
2025-01-08 14:53 ` Alejandro Lucero Palau
2025-01-14 23:59 ` Dan Williams
2024-12-16 16:10 ` [PATCH v8 03/27] cxl: add capabilities field to cxl_dev_state and cxl_port alejandro.lucero-palau
2024-12-24 17:08 ` Jonathan Cameron
2024-12-27 7:07 ` Alejandro Lucero Palau
2025-01-02 12:49 ` Jonathan Cameron
2025-01-03 7:16 ` Alejandro Lucero Palau
2025-01-03 10:47 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 04/27] cxl/pci: add check for validating capabilities alejandro.lucero-palau
2024-12-24 17:15 ` Jonathan Cameron
2024-12-27 7:47 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 05/27] cxl: move pci generic code alejandro.lucero-palau
2024-12-24 17:19 ` Jonathan Cameron
2024-12-27 7:53 ` Alejandro Lucero Palau
2025-01-08 5:19 ` Dan Williams
2025-01-08 14:39 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 06/27] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2024-12-24 17:22 ` Jonathan Cameron
2024-12-27 8:04 ` Alejandro Lucero Palau
2024-12-30 9:01 ` Alejandro Lucero Palau
2025-01-06 10:41 ` Dan Carpenter
2025-01-06 15:19 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 07/27] sfc: use cxl api for regs setup and checking alejandro.lucero-palau
2024-12-24 17:23 ` Jonathan Cameron
2024-12-27 8:05 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 08/27] cxl: add functions for resource request/release by a driver alejandro.lucero-palau
2024-12-24 17:25 ` Jonathan Cameron
2024-12-27 8:06 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 09/27] sfc: request cxl ram resource alejandro.lucero-palau
2024-12-24 17:27 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 10/27] resource: harden resource_contains alejandro.lucero-palau
2024-12-24 17:27 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 11/27] cxl: add function for setting media ready by a driver alejandro.lucero-palau
2024-12-24 17:29 ` Jonathan Cameron
2024-12-27 8:08 ` Alejandro Lucero Palau
2025-01-02 12:45 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 12/27] sfc: set cxl media ready alejandro.lucero-palau
2024-12-16 16:10 ` [PATCH v8 13/27] cxl: prepare memdev creation for type2 alejandro.lucero-palau
2024-12-24 17:32 ` Jonathan Cameron
2024-12-27 8:28 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 14/27] sfc: create type2 cxl memdev alejandro.lucero-palau
2024-12-24 17:33 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 15/27] cxl: define a driver interface for HPA free space enumeration alejandro.lucero-palau
2024-12-24 17:42 ` Jonathan Cameron
2024-12-27 10:05 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 16/27] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2024-12-18 11:17 ` Edward Cree
2024-12-24 17:43 ` Jonathan Cameron
2024-12-25 20:21 ` kernel test robot
2024-12-16 16:10 ` [PATCH v8 17/27] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2024-12-24 17:53 ` Jonathan Cameron [this message]
2024-12-27 10:23 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 18/27] sfc: get endpoint decoder alejandro.lucero-palau
2024-12-17 10:42 ` Simon Horman
2024-12-18 8:22 ` Alejandro Lucero Palau
2025-01-07 11:34 ` Simon Horman
2024-12-16 16:10 ` [PATCH v8 19/27] cxl: make region type based on endpoint type alejandro.lucero-palau
2024-12-24 17:54 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 20/27] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2024-12-24 17:56 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 21/27] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2024-12-24 17:56 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 22/27] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2024-12-24 18:01 ` Jonathan Cameron
2024-12-27 10:27 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 23/27] cxl: add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2024-12-24 18:04 ` Jonathan Cameron
2024-12-27 8:46 ` Alejandro Lucero Palau
2024-12-16 16:10 ` [PATCH v8 24/27] sfc: create cxl region alejandro.lucero-palau
2024-12-24 18:05 ` Jonathan Cameron
2024-12-25 23:58 ` kernel test robot
2024-12-16 16:10 ` [PATCH v8 25/27] cxl: add function for obtaining region range alejandro.lucero-palau
2024-12-24 18:07 ` Jonathan Cameron
2024-12-16 16:10 ` [PATCH v8 26/27] sfc: update MCDI protocol headers alejandro.lucero-palau
2024-12-16 16:10 ` [PATCH v8 27/27] sfc: support pio mapping based on cxl alejandro.lucero-palau
2024-12-17 10:47 ` Simon Horman
2024-12-18 8:32 ` Alejandro Lucero Palau
2024-12-30 12:16 ` Alejandro Lucero Palau
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