Re: [PATCH v9 03/27] cxl: add capabilities field to cxl_dev_state and cxl_port

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

On Mon, 30 Dec 2024 21:44:21 +0000
<alejandro.lucero-palau@amd.com> wrote:

> From: Alejandro Lucero <alucerop@amd.com>
> 
> Type2 devices have some Type3 functionalities as optional like an mbox
> or an hdm decoder, and CXL core needs a way to know what an CXL accelerator
> implements.
> 
> Add a new field to cxl_dev_state for keeping device capabilities as
> discovered during initialization. Add same field to cxl_port as registers
> discovery is also used during port initialization.
> 
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
> Reviewed-by: Fan Ni <fan.ni@samsung.com>
Comment in thread on v8.  I don't see a reason to have any specific
bitmap length - just use a final entry in the enum without a value set
to let us know how long it actually is.

Using the bit / bitmap functions should work fine without constraining
that to any particular value - also allowing for greater than 64 entries
with no need to fix up call sites etc.


> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> index 59cb35b40c7e..144ae9eb6253 100644
> --- a/drivers/cxl/core/regs.c
> +++ b/drivers/cxl/core/regs.c
> @@ -4,6 +4,7 @@

> +enum cxl_dev_cap {
> +	/* capabilities from Component Registers */
> +	CXL_DEV_CAP_RAS,
> +	CXL_DEV_CAP_HDM,
> +	/* capabilities from Device Registers */
> +	CXL_DEV_CAP_DEV_STATUS,
> +	CXL_DEV_CAP_MAILBOX_PRIMARY,
> +	CXL_DEV_CAP_MEMDEV,
> +	CXL_MAX_CAPS = 64
As in v8. I'm not seeing any reason for this.  If you need
a bitmap to be a particular number of unsigned longs, then that
code should be fixed. (only exception being compile time constant
bitmaps where this is tricky to do!)

Obviously I replied with that to v8 after you posted this
so time machines aside no way you could have acted on it yet.


Jonathan

> +};
> +
>  struct cxl_dev_state;
>  struct device;
>