[linux-next:master 3630/5236] drivers/accel/amdxdna/npu6_regs.c:76:31: sparse: sparse: symbol 'npu6_dev_priv' was not declared. Should it be static?

[kernel test robot <lkp@intel.com>]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head:   8155b4ef3466f0e289e8fcc9e6e62f3f4dceeac2
commit: 273b5176ac178d0d890cc1785d3688dc6f8adf37 [3630/5236] accel/amdxdna: Add RyzenAI-npu6 support
config: x86_64-randconfig-122-20241231 (https://download.01.org/0day-ci/archive/20250104/202501040316.PChncpYi-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250104/202501040316.PChncpYi-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202501040316.PChncpYi-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
>> drivers/accel/amdxdna/npu6_regs.c:76:31: sparse: sparse: symbol 'npu6_dev_priv' was not declared. Should it be static?

vim +/npu6_dev_priv +76 drivers/accel/amdxdna/npu6_regs.c

    75	
  > 76	const struct amdxdna_dev_priv npu6_dev_priv = {
    77		.fw_path        = "amdnpu/17f0_10/npu.sbin",
    78		.protocol_major = 0x6,
    79		.protocol_minor = 12,
    80		.rt_config	= {NPU6_RT_CFG_TYPE_PDI_LOAD, NPU6_RT_CFG_VAL_PDI_LOAD_APP},
    81		.col_align	= COL_ALIGN_NATURE,
    82		.mbox_dev_addr  = NPU6_MBOX_BAR_BASE,
    83		.mbox_size      = 0, /* Use BAR size */
    84		.sram_dev_addr  = NPU6_SRAM_BAR_BASE,
    85		.sram_offs      = {
    86			DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
    87			DEFINE_BAR_OFFSET(FW_ALIVE_OFF,   NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),
    88		},
    89		.psp_regs_off   = {
    90			DEFINE_BAR_OFFSET(PSP_CMD_REG,    NPU6_PSP, MP0_C2PMSG_123),
    91			DEFINE_BAR_OFFSET(PSP_ARG0_REG,   NPU6_REG, MPNPU_PUB_SCRATCH3),
    92			DEFINE_BAR_OFFSET(PSP_ARG1_REG,   NPU6_REG, MPNPU_PUB_SCRATCH4),
    93			DEFINE_BAR_OFFSET(PSP_ARG2_REG,   NPU6_REG, MPNPU_PUB_SCRATCH9),
    94			DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU6_PSP, MP0_C2PMSG_73),
    95			DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU6_PSP, MP0_C2PMSG_123),
    96			DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU6_REG, MPNPU_PUB_SCRATCH3),
    97		},
    98		.smu_regs_off   = {
    99			DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU6_SMU, MP1_C2PMSG_0),
   100			DEFINE_BAR_OFFSET(SMU_ARG_REG,  NPU6_SMU, MP1_C2PMSG_60),
   101			DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU6_SMU, MMNPU_APERTURE4_BASE),
   102			DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU6_SMU, MP1_C2PMSG_61),
   103			DEFINE_BAR_OFFSET(SMU_OUT_REG,  NPU6_SMU, MP1_C2PMSG_60),
   104		},
   105	};
   106	

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