* Re: [PATCH V1 6/6] spi: tegra210-quad: Introduce native DMA support
@ 2025-01-04 21:00 kernel test robot
0 siblings, 0 replies; 5+ messages in thread
From: kernel test robot @ 2025-01-04 21:00 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp, Dan Carpenter
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20250103060407.1064107-7-va@nvidia.com>
References: <20250103060407.1064107-7-va@nvidia.com>
TO: Vishwaroop A <va@nvidia.com>
TO: thierry.reding@gmail.com
TO: jonathanh@nvidia.com
TO: skomatineni@nvidia.com
TO: ldewangan@nvidia.com
TO: broonie@kernel.org
TO: linux-spi@vger.kernel.org
TO: linux-tegra@vger.kernel.org
TO: linux-kernel@vger.kernel.org
TO: kyarlagadda@nvidia.com
TO: smangipudi@nvidia.com
CC: va@nvidia.com
Hi Vishwaroop,
kernel test robot noticed the following build warnings:
[auto build test WARNING on broonie-spi/for-next]
[also build test WARNING on robh/for-next broonie-sound/for-next linus/master v6.13-rc5 next-20241220]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Vishwaroop-A/arm64-tegra-Configure-QSPI-clocks-and-add-DMA/20250103-141217
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
patch link: https://lore.kernel.org/r/20250103060407.1064107-7-va%40nvidia.com
patch subject: [PATCH V1 6/6] spi: tegra210-quad: Introduce native DMA support
:::::: branch date: 2 days ago
:::::: commit date: 2 days ago
config: hexagon-randconfig-r072-20250104 (https://download.01.org/0day-ci/archive/20250105/202501050449.DliDXUbw-lkp@intel.com/config)
compiler: clang version 20.0.0git (https://github.com/llvm/llvm-project 096551537b2a747a3387726ca618ceeb3950e9bc)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Closes: https://lore.kernel.org/r/202501050449.DliDXUbw-lkp@intel.com/
smatch warnings:
drivers/spi/spi-tegra210-quad.c:721 tegra_qspi_start_dma_based_transfer() warn: right shifting more than type allows 32 vs 32
vim +721 drivers/spi/spi-tegra210-quad.c
921fc1838fb036 Sowjanya Komatineni 2020-12-21 616
921fc1838fb036 Sowjanya Komatineni 2020-12-21 617 static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct spi_transfer *t)
921fc1838fb036 Sowjanya Komatineni 2020-12-21 618 {
921fc1838fb036 Sowjanya Komatineni 2020-12-21 619 struct dma_slave_config dma_sconfig = { 0 };
5c423922546fcf Vishwaroop A 2025-01-03 620 dma_addr_t rx_dma_phys, tx_dma_phys;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 621 unsigned int len;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 622 u8 dma_burst;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 623 int ret = 0;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 624 u32 val;
5c423922546fcf Vishwaroop A 2025-01-03 625 bool has_ext_dma = tqspi->soc_data->has_ext_dma;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 626
921fc1838fb036 Sowjanya Komatineni 2020-12-21 627 if (tqspi->is_packed) {
921fc1838fb036 Sowjanya Komatineni 2020-12-21 628 ret = tegra_qspi_dma_map_xfer(tqspi, t);
921fc1838fb036 Sowjanya Komatineni 2020-12-21 629 if (ret < 0)
921fc1838fb036 Sowjanya Komatineni 2020-12-21 630 return ret;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 631 }
921fc1838fb036 Sowjanya Komatineni 2020-12-21 632
921fc1838fb036 Sowjanya Komatineni 2020-12-21 633 val = QSPI_DMA_BLK_SET(tqspi->curr_dma_words - 1);
921fc1838fb036 Sowjanya Komatineni 2020-12-21 634 tegra_qspi_writel(tqspi, val, QSPI_DMA_BLK);
921fc1838fb036 Sowjanya Komatineni 2020-12-21 635
921fc1838fb036 Sowjanya Komatineni 2020-12-21 636 tegra_qspi_unmask_irq(tqspi);
921fc1838fb036 Sowjanya Komatineni 2020-12-21 637
921fc1838fb036 Sowjanya Komatineni 2020-12-21 638 if (tqspi->is_packed)
921fc1838fb036 Sowjanya Komatineni 2020-12-21 639 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 640 else
921fc1838fb036 Sowjanya Komatineni 2020-12-21 641 len = tqspi->curr_dma_words * 4;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 642
921fc1838fb036 Sowjanya Komatineni 2020-12-21 643 /* set attention level based on length of transfer */
5c423922546fcf Vishwaroop A 2025-01-03 644 if (has_ext_dma) {
921fc1838fb036 Sowjanya Komatineni 2020-12-21 645 val = 0;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 646 if (len & 0xf) {
921fc1838fb036 Sowjanya Komatineni 2020-12-21 647 val |= QSPI_TX_TRIG_1 | QSPI_RX_TRIG_1;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 648 dma_burst = 1;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 649 } else if (((len) >> 4) & 0x1) {
921fc1838fb036 Sowjanya Komatineni 2020-12-21 650 val |= QSPI_TX_TRIG_4 | QSPI_RX_TRIG_4;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 651 dma_burst = 4;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 652 } else {
921fc1838fb036 Sowjanya Komatineni 2020-12-21 653 val |= QSPI_TX_TRIG_8 | QSPI_RX_TRIG_8;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 654 dma_burst = 8;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 655 }
921fc1838fb036 Sowjanya Komatineni 2020-12-21 656
921fc1838fb036 Sowjanya Komatineni 2020-12-21 657 tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL);
5c423922546fcf Vishwaroop A 2025-01-03 658 }
5c423922546fcf Vishwaroop A 2025-01-03 659
921fc1838fb036 Sowjanya Komatineni 2020-12-21 660 tqspi->dma_control_reg = val;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 661
921fc1838fb036 Sowjanya Komatineni 2020-12-21 662 dma_sconfig.device_fc = true;
5c423922546fcf Vishwaroop A 2025-01-03 663
5c423922546fcf Vishwaroop A 2025-01-03 664 if ((tqspi->cur_direction & DATA_DIR_TX)) {
5c423922546fcf Vishwaroop A 2025-01-03 665 if (has_ext_dma) {
921fc1838fb036 Sowjanya Komatineni 2020-12-21 666 dma_sconfig.dst_addr = tqspi->phys + QSPI_TX_FIFO;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 667 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 668 dma_sconfig.dst_maxburst = dma_burst;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 669 ret = dmaengine_slave_config(tqspi->tx_dma_chan, &dma_sconfig);
921fc1838fb036 Sowjanya Komatineni 2020-12-21 670 if (ret < 0) {
921fc1838fb036 Sowjanya Komatineni 2020-12-21 671 dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret);
921fc1838fb036 Sowjanya Komatineni 2020-12-21 672 return ret;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 673 }
921fc1838fb036 Sowjanya Komatineni 2020-12-21 674
921fc1838fb036 Sowjanya Komatineni 2020-12-21 675 tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t);
921fc1838fb036 Sowjanya Komatineni 2020-12-21 676 ret = tegra_qspi_start_tx_dma(tqspi, t, len);
921fc1838fb036 Sowjanya Komatineni 2020-12-21 677 if (ret < 0) {
921fc1838fb036 Sowjanya Komatineni 2020-12-21 678 dev_err(tqspi->dev, "failed to starting TX DMA: %d\n", ret);
921fc1838fb036 Sowjanya Komatineni 2020-12-21 679 return ret;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 680 }
5c423922546fcf Vishwaroop A 2025-01-03 681 } else {
5c423922546fcf Vishwaroop A 2025-01-03 682 if (tqspi->is_packed)
5c423922546fcf Vishwaroop A 2025-01-03 683 tx_dma_phys = t->tx_dma;
5c423922546fcf Vishwaroop A 2025-01-03 684 else
5c423922546fcf Vishwaroop A 2025-01-03 685 tx_dma_phys = tqspi->tx_dma_phys;
5c423922546fcf Vishwaroop A 2025-01-03 686 tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t);
5c423922546fcf Vishwaroop A 2025-01-03 687 tegra_qspi_writel(tqspi, lower_32_bits(tx_dma_phys),
5c423922546fcf Vishwaroop A 2025-01-03 688 QSPI_DMA_MEM_ADDRESS_REG);
5c423922546fcf Vishwaroop A 2025-01-03 689 tegra_qspi_writel(tqspi, (upper_32_bits(tx_dma_phys) & 0xff),
5c423922546fcf Vishwaroop A 2025-01-03 690 QSPI_DMA_HI_ADDRESS_REG);
5c423922546fcf Vishwaroop A 2025-01-03 691 }
921fc1838fb036 Sowjanya Komatineni 2020-12-21 692 }
921fc1838fb036 Sowjanya Komatineni 2020-12-21 693
921fc1838fb036 Sowjanya Komatineni 2020-12-21 694 if (tqspi->cur_direction & DATA_DIR_RX) {
5c423922546fcf Vishwaroop A 2025-01-03 695 if (has_ext_dma) {
921fc1838fb036 Sowjanya Komatineni 2020-12-21 696 dma_sconfig.src_addr = tqspi->phys + QSPI_RX_FIFO;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 697 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 698 dma_sconfig.src_maxburst = dma_burst;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 699 ret = dmaengine_slave_config(tqspi->rx_dma_chan, &dma_sconfig);
921fc1838fb036 Sowjanya Komatineni 2020-12-21 700 if (ret < 0) {
921fc1838fb036 Sowjanya Komatineni 2020-12-21 701 dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret);
921fc1838fb036 Sowjanya Komatineni 2020-12-21 702 return ret;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 703 }
921fc1838fb036 Sowjanya Komatineni 2020-12-21 704 dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys,
5c423922546fcf Vishwaroop A 2025-01-03 705 tqspi->dma_buf_size, DMA_FROM_DEVICE);
921fc1838fb036 Sowjanya Komatineni 2020-12-21 706 ret = tegra_qspi_start_rx_dma(tqspi, t, len);
921fc1838fb036 Sowjanya Komatineni 2020-12-21 707 if (ret < 0) {
921fc1838fb036 Sowjanya Komatineni 2020-12-21 708 dev_err(tqspi->dev, "failed to start RX DMA: %d\n", ret);
921fc1838fb036 Sowjanya Komatineni 2020-12-21 709 if (tqspi->cur_direction & DATA_DIR_TX)
921fc1838fb036 Sowjanya Komatineni 2020-12-21 710 dmaengine_terminate_all(tqspi->tx_dma_chan);
921fc1838fb036 Sowjanya Komatineni 2020-12-21 711 return ret;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 712 }
5c423922546fcf Vishwaroop A 2025-01-03 713 } else {
5c423922546fcf Vishwaroop A 2025-01-03 714 if (tqspi->is_packed)
5c423922546fcf Vishwaroop A 2025-01-03 715 rx_dma_phys = t->rx_dma;
5c423922546fcf Vishwaroop A 2025-01-03 716 else
5c423922546fcf Vishwaroop A 2025-01-03 717 rx_dma_phys = tqspi->rx_dma_phys;
5c423922546fcf Vishwaroop A 2025-01-03 718
5c423922546fcf Vishwaroop A 2025-01-03 719 tegra_qspi_writel(tqspi, (rx_dma_phys & 0xffffffff),
5c423922546fcf Vishwaroop A 2025-01-03 720 QSPI_DMA_MEM_ADDRESS_REG);
5c423922546fcf Vishwaroop A 2025-01-03 @721 tegra_qspi_writel(tqspi, ((rx_dma_phys >> 32) & 0xff),
5c423922546fcf Vishwaroop A 2025-01-03 722 QSPI_DMA_HI_ADDRESS_REG);
5c423922546fcf Vishwaroop A 2025-01-03 723 }
921fc1838fb036 Sowjanya Komatineni 2020-12-21 724 }
921fc1838fb036 Sowjanya Komatineni 2020-12-21 725
921fc1838fb036 Sowjanya Komatineni 2020-12-21 726 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1);
921fc1838fb036 Sowjanya Komatineni 2020-12-21 727
921fc1838fb036 Sowjanya Komatineni 2020-12-21 728 tqspi->is_curr_dma_xfer = true;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 729 tqspi->dma_control_reg = val;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 730 val |= QSPI_DMA_EN;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 731 tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL);
921fc1838fb036 Sowjanya Komatineni 2020-12-21 732
921fc1838fb036 Sowjanya Komatineni 2020-12-21 733 return ret;
921fc1838fb036 Sowjanya Komatineni 2020-12-21 734 }
921fc1838fb036 Sowjanya Komatineni 2020-12-21 735
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 0/6] Configure Clocks, Add Native Dma support. @ 2025-01-03 6:04 Vishwaroop A 2025-01-03 6:04 ` [PATCH V1 6/6] spi: tegra210-quad: Introduce native DMA support Vishwaroop A 0 siblings, 1 reply; 5+ messages in thread From: Vishwaroop A @ 2025-01-03 6:04 UTC (permalink / raw) To: thierry.reding, jonathanh, skomatineni, ldewangan, broonie, linux-spi, linux-tegra, linux-kernel, kyarlagadda, smangipudi Cc: va This patch series configures qspi clocks, fixes combined sequence programming and introduces native dma support. Vishwaroop A (6): arm64: tegra: Configure QSPI clocks and add DMA spi: tegra210-quad: Update dummy sequence configuration spi: tegra210-quad: Fix X1_X2_X4 encoding and support x4 transfers spi: tegra210-quad: remove redundant error handling code spi: tegra210-quad: modify chip select (CS) deactivation spi: tegra210-quad: Introduce native DMA support arch/arm64/boot/dts/nvidia/tegra234.dtsi | 14 ++ drivers/spi/spi-tegra210-quad.c | 273 +++++++++++++---------- 2 files changed, 174 insertions(+), 113 deletions(-) -- 2.17.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH V1 6/6] spi: tegra210-quad: Introduce native DMA support 2025-01-03 6:04 [PATCH 0/6] Configure Clocks, Add Native Dma support Vishwaroop A @ 2025-01-03 6:04 ` Vishwaroop A 2025-01-03 14:21 ` kernel test robot ` (2 more replies) 0 siblings, 3 replies; 5+ messages in thread From: Vishwaroop A @ 2025-01-03 6:04 UTC (permalink / raw) To: thierry.reding, jonathanh, skomatineni, ldewangan, broonie, linux-spi, linux-tegra, linux-kernel, kyarlagadda, smangipudi Cc: va Previous generations of Tegra supported DMA operations by an external DMA controller, but the QSPI on Tegra234 devices now have an internal DMA controller. Internal DMA: Uses the QSPI controller's built-in DMA engine, which is limited in capabilities and tied directly to the QSPI module. External DMA: Utilizes a separate, GPCDMA DMA controller that can transfer data between QSPI and any memory location. Native DMA Initialization: Introduce routines to initialize and configure native DMA channels for both transmit and receive paths. Set up DMA mapping functions to manage buffer addresses effectively. Enhance Transfer Logic: Implement logic to choose between CPU-based and DMA-based transfers based on data size. Change-Id: Icf3ef4767947cef67821c092ecd9ea6bccb2a4e4 Signed-off-by: Vishwaroop A <va@nvidia.com> --- drivers/spi/spi-tegra210-quad.c | 218 ++++++++++++++++++-------------- 1 file changed, 126 insertions(+), 92 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 04f41e92c1e2..066caee85c52 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -111,6 +111,9 @@ #define QSPI_DMA_BLK 0x024 #define QSPI_DMA_BLK_SET(x) (((x) & 0xffff) << 0) +#define QSPI_DMA_MEM_ADDRESS_REG 0x028 +#define QSPI_DMA_HI_ADDRESS_REG 0x02c + #define QSPI_TX_FIFO 0x108 #define QSPI_RX_FIFO 0x188 @@ -167,9 +170,9 @@ enum tegra_qspi_transfer_type { }; struct tegra_qspi_soc_data { - bool has_dma; bool cmb_xfer_capable; bool supports_tpm; + bool has_ext_dma; unsigned int cs_count; }; @@ -605,17 +608,21 @@ static void tegra_qspi_dma_unmap_xfer(struct tegra_qspi *tqspi, struct spi_trans len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; - dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); - dma_unmap_single(tqspi->dev, t->rx_dma, len, DMA_FROM_DEVICE); + if (t->tx_buf) + dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); + if (t->rx_buf) + dma_unmap_single(tqspi->dev, t->rx_dma, len, DMA_FROM_DEVICE); } static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct spi_transfer *t) { struct dma_slave_config dma_sconfig = { 0 }; + dma_addr_t rx_dma_phys, tx_dma_phys; unsigned int len; u8 dma_burst; int ret = 0; u32 val; + bool has_ext_dma = tqspi->soc_data->has_ext_dma; if (tqspi->is_packed) { ret = tegra_qspi_dma_map_xfer(tqspi, t); @@ -634,60 +641,85 @@ static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct len = tqspi->curr_dma_words * 4; /* set attention level based on length of transfer */ - val = 0; - if (len & 0xf) { - val |= QSPI_TX_TRIG_1 | QSPI_RX_TRIG_1; - dma_burst = 1; - } else if (((len) >> 4) & 0x1) { - val |= QSPI_TX_TRIG_4 | QSPI_RX_TRIG_4; - dma_burst = 4; - } else { - val |= QSPI_TX_TRIG_8 | QSPI_RX_TRIG_8; - dma_burst = 8; + if (has_ext_dma) { + val = 0; + if (len & 0xf) { + val |= QSPI_TX_TRIG_1 | QSPI_RX_TRIG_1; + dma_burst = 1; + } else if (((len) >> 4) & 0x1) { + val |= QSPI_TX_TRIG_4 | QSPI_RX_TRIG_4; + dma_burst = 4; + } else { + val |= QSPI_TX_TRIG_8 | QSPI_RX_TRIG_8; + dma_burst = 8; + } + + tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL); } - tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL); tqspi->dma_control_reg = val; dma_sconfig.device_fc = true; - if (tqspi->cur_direction & DATA_DIR_TX) { - dma_sconfig.dst_addr = tqspi->phys + QSPI_TX_FIFO; - dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; - dma_sconfig.dst_maxburst = dma_burst; - ret = dmaengine_slave_config(tqspi->tx_dma_chan, &dma_sconfig); - if (ret < 0) { - dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); - return ret; - } - tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t); - ret = tegra_qspi_start_tx_dma(tqspi, t, len); - if (ret < 0) { - dev_err(tqspi->dev, "failed to starting TX DMA: %d\n", ret); - return ret; + if ((tqspi->cur_direction & DATA_DIR_TX)) { + if (has_ext_dma) { + dma_sconfig.dst_addr = tqspi->phys + QSPI_TX_FIFO; + dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + dma_sconfig.dst_maxburst = dma_burst; + ret = dmaengine_slave_config(tqspi->tx_dma_chan, &dma_sconfig); + if (ret < 0) { + dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); + return ret; + } + + tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t); + ret = tegra_qspi_start_tx_dma(tqspi, t, len); + if (ret < 0) { + dev_err(tqspi->dev, "failed to starting TX DMA: %d\n", ret); + return ret; + } + } else { + if (tqspi->is_packed) + tx_dma_phys = t->tx_dma; + else + tx_dma_phys = tqspi->tx_dma_phys; + tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t); + tegra_qspi_writel(tqspi, lower_32_bits(tx_dma_phys), + QSPI_DMA_MEM_ADDRESS_REG); + tegra_qspi_writel(tqspi, (upper_32_bits(tx_dma_phys) & 0xff), + QSPI_DMA_HI_ADDRESS_REG); } } if (tqspi->cur_direction & DATA_DIR_RX) { - dma_sconfig.src_addr = tqspi->phys + QSPI_RX_FIFO; - dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; - dma_sconfig.src_maxburst = dma_burst; - ret = dmaengine_slave_config(tqspi->rx_dma_chan, &dma_sconfig); - if (ret < 0) { - dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); - return ret; - } - - dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, - tqspi->dma_buf_size, - DMA_FROM_DEVICE); - - ret = tegra_qspi_start_rx_dma(tqspi, t, len); - if (ret < 0) { - dev_err(tqspi->dev, "failed to start RX DMA: %d\n", ret); - if (tqspi->cur_direction & DATA_DIR_TX) - dmaengine_terminate_all(tqspi->tx_dma_chan); - return ret; + if (has_ext_dma) { + dma_sconfig.src_addr = tqspi->phys + QSPI_RX_FIFO; + dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + dma_sconfig.src_maxburst = dma_burst; + ret = dmaengine_slave_config(tqspi->rx_dma_chan, &dma_sconfig); + if (ret < 0) { + dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); + return ret; + } + dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, + tqspi->dma_buf_size, DMA_FROM_DEVICE); + ret = tegra_qspi_start_rx_dma(tqspi, t, len); + if (ret < 0) { + dev_err(tqspi->dev, "failed to start RX DMA: %d\n", ret); + if (tqspi->cur_direction & DATA_DIR_TX) + dmaengine_terminate_all(tqspi->tx_dma_chan); + return ret; + } + } else { + if (tqspi->is_packed) + rx_dma_phys = t->rx_dma; + else + rx_dma_phys = tqspi->rx_dma_phys; + + tegra_qspi_writel(tqspi, (rx_dma_phys & 0xffffffff), + QSPI_DMA_MEM_ADDRESS_REG); + tegra_qspi_writel(tqspi, ((rx_dma_phys >> 32) & 0xff), + QSPI_DMA_HI_ADDRESS_REG); } } @@ -726,9 +758,6 @@ static int tegra_qspi_start_cpu_based_transfer(struct tegra_qspi *qspi, struct s static void tegra_qspi_deinit_dma(struct tegra_qspi *tqspi) { - if (!tqspi->soc_data->has_dma) - return; - if (tqspi->tx_dma_buf) { dma_free_coherent(tqspi->dev, tqspi->dma_buf_size, tqspi->tx_dma_buf, tqspi->tx_dma_phys); @@ -759,16 +788,26 @@ static int tegra_qspi_init_dma(struct tegra_qspi *tqspi) u32 *dma_buf; int err; - if (!tqspi->soc_data->has_dma) - return 0; + if (tqspi->soc_data->has_ext_dma) { + dma_chan = dma_request_chan(tqspi->dev, "rx"); + if (IS_ERR(dma_chan)) { + err = PTR_ERR(dma_chan); + goto err_out; + } - dma_chan = dma_request_chan(tqspi->dev, "rx"); - if (IS_ERR(dma_chan)) { - err = PTR_ERR(dma_chan); - goto err_out; - } + tqspi->rx_dma_chan = dma_chan; - tqspi->rx_dma_chan = dma_chan; + dma_chan = dma_request_chan(tqspi->dev, "tx"); + if (IS_ERR(dma_chan)) { + err = PTR_ERR(dma_chan); + goto err_out; + } + + tqspi->tx_dma_chan = dma_chan; + } else { + tqspi->rx_dma_chan = NULL; + tqspi->tx_dma_chan = NULL; + } dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL); if (!dma_buf) { @@ -779,14 +818,6 @@ static int tegra_qspi_init_dma(struct tegra_qspi *tqspi) tqspi->rx_dma_buf = dma_buf; tqspi->rx_dma_phys = dma_phys; - dma_chan = dma_request_chan(tqspi->dev, "tx"); - if (IS_ERR(dma_chan)) { - err = PTR_ERR(dma_chan); - goto err_out; - } - - tqspi->tx_dma_chan = dma_chan; - dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL); if (!dma_buf) { err = -ENOMEM; @@ -1056,6 +1087,7 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, struct spi_message *msg) { bool is_first_msg = true; + bool has_ext_dma = tqspi->soc_data->has_ext_dma; struct spi_transfer *xfer; struct spi_device *spi = msg->spi; u8 transfer_phase = 0; @@ -1128,15 +1160,12 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, if (WARN_ON(ret == 0)) { dev_err(tqspi->dev, "QSPI Transfer failed with timeout: %d\n", ret); - if (tqspi->is_curr_dma_xfer && - (tqspi->cur_direction & DATA_DIR_TX)) - dmaengine_terminate_all - (tqspi->tx_dma_chan); - - if (tqspi->is_curr_dma_xfer && - (tqspi->cur_direction & DATA_DIR_RX)) - dmaengine_terminate_all - (tqspi->rx_dma_chan); + if (tqspi->is_curr_dma_xfer && has_ext_dma) { + if (tqspi->cur_direction & DATA_DIR_TX) + dmaengine_terminate_all(tqspi->tx_dma_chan); + if (tqspi->cur_direction & DATA_DIR_RX) + dmaengine_terminate_all(tqspi->rx_dma_chan); + } /* Abort transfer by resetting pio/dma bit */ if (!tqspi->is_curr_dma_xfer) { @@ -1197,6 +1226,7 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi, struct spi_device *spi = msg->spi; struct spi_transfer *transfer; bool is_first_msg = true; + bool has_ext_dma = tqspi->soc_data->has_ext_dma; int ret = 0, val = 0; msg->status = 0; @@ -1251,10 +1281,12 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi, QSPI_DMA_TIMEOUT); if (WARN_ON(ret == 0)) { dev_err(tqspi->dev, "transfer timeout\n"); - if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_TX)) - dmaengine_terminate_all(tqspi->tx_dma_chan); - if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_RX)) - dmaengine_terminate_all(tqspi->rx_dma_chan); + if (tqspi->is_curr_dma_xfer && has_ext_dma) { + if (tqspi->cur_direction & DATA_DIR_TX) + dmaengine_terminate_all(tqspi->tx_dma_chan); + if (tqspi->cur_direction & DATA_DIR_RX) + dmaengine_terminate_all(tqspi->rx_dma_chan); + } tegra_qspi_handle_error(tqspi); ret = -EIO; goto complete_xfer; @@ -1323,7 +1355,7 @@ static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi, return false; xfer = list_next_entry(xfer, transfer_list); } - if (!tqspi->soc_data->has_dma && xfer->len > (QSPI_FIFO_DEPTH << 2)) + if (!tqspi->soc_data->has_ext_dma && xfer->len > (QSPI_FIFO_DEPTH << 2)) return false; return true; @@ -1388,30 +1420,32 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi) if (tqspi->cur_direction & DATA_DIR_TX) { if (tqspi->tx_status) { - dmaengine_terminate_all(tqspi->tx_dma_chan); - err += 1; - } else { + if (tqspi->tx_dma_chan) + dmaengine_terminate_all(tqspi->tx_dma_chan); + err++; + } else if (tqspi->tx_dma_chan) { wait_status = wait_for_completion_interruptible_timeout( &tqspi->tx_dma_complete, QSPI_DMA_TIMEOUT); if (wait_status <= 0) { dmaengine_terminate_all(tqspi->tx_dma_chan); dev_err(tqspi->dev, "failed TX DMA transfer\n"); - err += 1; + err++; } } } if (tqspi->cur_direction & DATA_DIR_RX) { if (tqspi->rx_status) { - dmaengine_terminate_all(tqspi->rx_dma_chan); - err += 2; - } else { + if (tqspi->rx_dma_chan) + dmaengine_terminate_all(tqspi->rx_dma_chan); + err++; + } else if (tqspi->rx_dma_chan) { wait_status = wait_for_completion_interruptible_timeout( &tqspi->rx_dma_complete, QSPI_DMA_TIMEOUT); if (wait_status <= 0) { dmaengine_terminate_all(tqspi->rx_dma_chan); dev_err(tqspi->dev, "failed RX DMA transfer\n"); - err += 2; + err++; } } } @@ -1474,28 +1508,28 @@ static irqreturn_t tegra_qspi_isr_thread(int irq, void *context_data) } static struct tegra_qspi_soc_data tegra210_qspi_soc_data = { - .has_dma = true, + .has_ext_dma = true, .cmb_xfer_capable = false, .supports_tpm = false, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra186_qspi_soc_data = { - .has_dma = true, + .has_ext_dma = true, .cmb_xfer_capable = true, .supports_tpm = false, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra234_qspi_soc_data = { - .has_dma = false, + .has_ext_dma = false, .cmb_xfer_capable = true, .supports_tpm = true, .cs_count = 1, }; static struct tegra_qspi_soc_data tegra241_qspi_soc_data = { - .has_dma = false, + .has_ext_dma = true, .cmb_xfer_capable = true, .supports_tpm = true, .cs_count = 4, -- 2.17.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH V1 6/6] spi: tegra210-quad: Introduce native DMA support 2025-01-03 6:04 ` [PATCH V1 6/6] spi: tegra210-quad: Introduce native DMA support Vishwaroop A @ 2025-01-03 14:21 ` kernel test robot 2025-01-03 23:16 ` kernel test robot 2025-01-06 13:04 ` Mark Brown 2 siblings, 0 replies; 5+ messages in thread From: kernel test robot @ 2025-01-03 14:21 UTC (permalink / raw) To: Vishwaroop A, thierry.reding, jonathanh, skomatineni, ldewangan, broonie, linux-spi, linux-tegra, linux-kernel, kyarlagadda, smangipudi Cc: oe-kbuild-all, va Hi Vishwaroop, kernel test robot noticed the following build warnings: [auto build test WARNING on broonie-spi/for-next] [also build test WARNING on robh/for-next broonie-sound/for-next linus/master v6.13-rc5 next-20241220] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Vishwaroop-A/arm64-tegra-Configure-QSPI-clocks-and-add-DMA/20250103-141217 base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next patch link: https://lore.kernel.org/r/20250103060407.1064107-7-va%40nvidia.com patch subject: [PATCH V1 6/6] spi: tegra210-quad: Introduce native DMA support config: sparc-randconfig-002-20250103 (https://download.01.org/0day-ci/archive/20250103/202501032202.m6t4wlQB-lkp@intel.com/config) compiler: sparc-linux-gcc (GCC) 14.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250103/202501032202.m6t4wlQB-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202501032202.m6t4wlQB-lkp@intel.com/ All warnings (new ones prefixed by >>): drivers/spi/spi-tegra210-quad.c: In function 'tegra_qspi_start_dma_based_transfer': >> drivers/spi/spi-tegra210-quad.c:721:64: warning: right shift count >= width of type [-Wshift-count-overflow] 721 | tegra_qspi_writel(tqspi, ((rx_dma_phys >> 32) & 0xff), | ^~ vim +721 drivers/spi/spi-tegra210-quad.c 616 617 static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct spi_transfer *t) 618 { 619 struct dma_slave_config dma_sconfig = { 0 }; 620 dma_addr_t rx_dma_phys, tx_dma_phys; 621 unsigned int len; 622 u8 dma_burst; 623 int ret = 0; 624 u32 val; 625 bool has_ext_dma = tqspi->soc_data->has_ext_dma; 626 627 if (tqspi->is_packed) { 628 ret = tegra_qspi_dma_map_xfer(tqspi, t); 629 if (ret < 0) 630 return ret; 631 } 632 633 val = QSPI_DMA_BLK_SET(tqspi->curr_dma_words - 1); 634 tegra_qspi_writel(tqspi, val, QSPI_DMA_BLK); 635 636 tegra_qspi_unmask_irq(tqspi); 637 638 if (tqspi->is_packed) 639 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; 640 else 641 len = tqspi->curr_dma_words * 4; 642 643 /* set attention level based on length of transfer */ 644 if (has_ext_dma) { 645 val = 0; 646 if (len & 0xf) { 647 val |= QSPI_TX_TRIG_1 | QSPI_RX_TRIG_1; 648 dma_burst = 1; 649 } else if (((len) >> 4) & 0x1) { 650 val |= QSPI_TX_TRIG_4 | QSPI_RX_TRIG_4; 651 dma_burst = 4; 652 } else { 653 val |= QSPI_TX_TRIG_8 | QSPI_RX_TRIG_8; 654 dma_burst = 8; 655 } 656 657 tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL); 658 } 659 660 tqspi->dma_control_reg = val; 661 662 dma_sconfig.device_fc = true; 663 664 if ((tqspi->cur_direction & DATA_DIR_TX)) { 665 if (has_ext_dma) { 666 dma_sconfig.dst_addr = tqspi->phys + QSPI_TX_FIFO; 667 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 668 dma_sconfig.dst_maxburst = dma_burst; 669 ret = dmaengine_slave_config(tqspi->tx_dma_chan, &dma_sconfig); 670 if (ret < 0) { 671 dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); 672 return ret; 673 } 674 675 tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t); 676 ret = tegra_qspi_start_tx_dma(tqspi, t, len); 677 if (ret < 0) { 678 dev_err(tqspi->dev, "failed to starting TX DMA: %d\n", ret); 679 return ret; 680 } 681 } else { 682 if (tqspi->is_packed) 683 tx_dma_phys = t->tx_dma; 684 else 685 tx_dma_phys = tqspi->tx_dma_phys; 686 tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t); 687 tegra_qspi_writel(tqspi, lower_32_bits(tx_dma_phys), 688 QSPI_DMA_MEM_ADDRESS_REG); 689 tegra_qspi_writel(tqspi, (upper_32_bits(tx_dma_phys) & 0xff), 690 QSPI_DMA_HI_ADDRESS_REG); 691 } 692 } 693 694 if (tqspi->cur_direction & DATA_DIR_RX) { 695 if (has_ext_dma) { 696 dma_sconfig.src_addr = tqspi->phys + QSPI_RX_FIFO; 697 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 698 dma_sconfig.src_maxburst = dma_burst; 699 ret = dmaengine_slave_config(tqspi->rx_dma_chan, &dma_sconfig); 700 if (ret < 0) { 701 dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); 702 return ret; 703 } 704 dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, 705 tqspi->dma_buf_size, DMA_FROM_DEVICE); 706 ret = tegra_qspi_start_rx_dma(tqspi, t, len); 707 if (ret < 0) { 708 dev_err(tqspi->dev, "failed to start RX DMA: %d\n", ret); 709 if (tqspi->cur_direction & DATA_DIR_TX) 710 dmaengine_terminate_all(tqspi->tx_dma_chan); 711 return ret; 712 } 713 } else { 714 if (tqspi->is_packed) 715 rx_dma_phys = t->rx_dma; 716 else 717 rx_dma_phys = tqspi->rx_dma_phys; 718 719 tegra_qspi_writel(tqspi, (rx_dma_phys & 0xffffffff), 720 QSPI_DMA_MEM_ADDRESS_REG); > 721 tegra_qspi_writel(tqspi, ((rx_dma_phys >> 32) & 0xff), 722 QSPI_DMA_HI_ADDRESS_REG); 723 } 724 } 725 726 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1); 727 728 tqspi->is_curr_dma_xfer = true; 729 tqspi->dma_control_reg = val; 730 val |= QSPI_DMA_EN; 731 tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL); 732 733 return ret; 734 } 735 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH V1 6/6] spi: tegra210-quad: Introduce native DMA support 2025-01-03 6:04 ` [PATCH V1 6/6] spi: tegra210-quad: Introduce native DMA support Vishwaroop A 2025-01-03 14:21 ` kernel test robot @ 2025-01-03 23:16 ` kernel test robot 2025-01-06 13:04 ` Mark Brown 2 siblings, 0 replies; 5+ messages in thread From: kernel test robot @ 2025-01-03 23:16 UTC (permalink / raw) To: Vishwaroop A, thierry.reding, jonathanh, skomatineni, ldewangan, broonie, linux-spi, linux-tegra, linux-kernel, kyarlagadda, smangipudi Cc: llvm, oe-kbuild-all, va Hi Vishwaroop, kernel test robot noticed the following build warnings: [auto build test WARNING on broonie-spi/for-next] [also build test WARNING on robh/for-next broonie-sound/for-next linus/master v6.13-rc5 next-20241220] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Vishwaroop-A/arm64-tegra-Configure-QSPI-clocks-and-add-DMA/20250103-141217 base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next patch link: https://lore.kernel.org/r/20250103060407.1064107-7-va%40nvidia.com patch subject: [PATCH V1 6/6] spi: tegra210-quad: Introduce native DMA support config: arm-randconfig-001-20250104 (https://download.01.org/0day-ci/archive/20250104/202501040605.Ndat3QJw-lkp@intel.com/config) compiler: clang version 20.0.0git (https://github.com/llvm/llvm-project 096551537b2a747a3387726ca618ceeb3950e9bc) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250104/202501040605.Ndat3QJw-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202501040605.Ndat3QJw-lkp@intel.com/ All warnings (new ones prefixed by >>): In file included from drivers/spi/spi-tegra210-quad.c:8: In file included from include/linux/dmaengine.h:12: In file included from include/linux/scatterlist.h:8: In file included from include/linux/mm.h:2223: include/linux/vmstat.h:518:36: warning: arithmetic between different enumeration types ('enum node_stat_item' and 'enum lru_list') [-Wenum-enum-conversion] 518 | return node_stat_name(NR_LRU_BASE + lru) + 3; // skip "nr_" | ~~~~~~~~~~~ ^ ~~~ >> drivers/spi/spi-tegra210-quad.c:721:43: warning: shift count >= width of type [-Wshift-count-overflow] 721 | tegra_qspi_writel(tqspi, ((rx_dma_phys >> 32) & 0xff), | ^ ~~ 2 warnings generated. vim +721 drivers/spi/spi-tegra210-quad.c 616 617 static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct spi_transfer *t) 618 { 619 struct dma_slave_config dma_sconfig = { 0 }; 620 dma_addr_t rx_dma_phys, tx_dma_phys; 621 unsigned int len; 622 u8 dma_burst; 623 int ret = 0; 624 u32 val; 625 bool has_ext_dma = tqspi->soc_data->has_ext_dma; 626 627 if (tqspi->is_packed) { 628 ret = tegra_qspi_dma_map_xfer(tqspi, t); 629 if (ret < 0) 630 return ret; 631 } 632 633 val = QSPI_DMA_BLK_SET(tqspi->curr_dma_words - 1); 634 tegra_qspi_writel(tqspi, val, QSPI_DMA_BLK); 635 636 tegra_qspi_unmask_irq(tqspi); 637 638 if (tqspi->is_packed) 639 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; 640 else 641 len = tqspi->curr_dma_words * 4; 642 643 /* set attention level based on length of transfer */ 644 if (has_ext_dma) { 645 val = 0; 646 if (len & 0xf) { 647 val |= QSPI_TX_TRIG_1 | QSPI_RX_TRIG_1; 648 dma_burst = 1; 649 } else if (((len) >> 4) & 0x1) { 650 val |= QSPI_TX_TRIG_4 | QSPI_RX_TRIG_4; 651 dma_burst = 4; 652 } else { 653 val |= QSPI_TX_TRIG_8 | QSPI_RX_TRIG_8; 654 dma_burst = 8; 655 } 656 657 tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL); 658 } 659 660 tqspi->dma_control_reg = val; 661 662 dma_sconfig.device_fc = true; 663 664 if ((tqspi->cur_direction & DATA_DIR_TX)) { 665 if (has_ext_dma) { 666 dma_sconfig.dst_addr = tqspi->phys + QSPI_TX_FIFO; 667 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 668 dma_sconfig.dst_maxburst = dma_burst; 669 ret = dmaengine_slave_config(tqspi->tx_dma_chan, &dma_sconfig); 670 if (ret < 0) { 671 dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); 672 return ret; 673 } 674 675 tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t); 676 ret = tegra_qspi_start_tx_dma(tqspi, t, len); 677 if (ret < 0) { 678 dev_err(tqspi->dev, "failed to starting TX DMA: %d\n", ret); 679 return ret; 680 } 681 } else { 682 if (tqspi->is_packed) 683 tx_dma_phys = t->tx_dma; 684 else 685 tx_dma_phys = tqspi->tx_dma_phys; 686 tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t); 687 tegra_qspi_writel(tqspi, lower_32_bits(tx_dma_phys), 688 QSPI_DMA_MEM_ADDRESS_REG); 689 tegra_qspi_writel(tqspi, (upper_32_bits(tx_dma_phys) & 0xff), 690 QSPI_DMA_HI_ADDRESS_REG); 691 } 692 } 693 694 if (tqspi->cur_direction & DATA_DIR_RX) { 695 if (has_ext_dma) { 696 dma_sconfig.src_addr = tqspi->phys + QSPI_RX_FIFO; 697 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 698 dma_sconfig.src_maxburst = dma_burst; 699 ret = dmaengine_slave_config(tqspi->rx_dma_chan, &dma_sconfig); 700 if (ret < 0) { 701 dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); 702 return ret; 703 } 704 dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, 705 tqspi->dma_buf_size, DMA_FROM_DEVICE); 706 ret = tegra_qspi_start_rx_dma(tqspi, t, len); 707 if (ret < 0) { 708 dev_err(tqspi->dev, "failed to start RX DMA: %d\n", ret); 709 if (tqspi->cur_direction & DATA_DIR_TX) 710 dmaengine_terminate_all(tqspi->tx_dma_chan); 711 return ret; 712 } 713 } else { 714 if (tqspi->is_packed) 715 rx_dma_phys = t->rx_dma; 716 else 717 rx_dma_phys = tqspi->rx_dma_phys; 718 719 tegra_qspi_writel(tqspi, (rx_dma_phys & 0xffffffff), 720 QSPI_DMA_MEM_ADDRESS_REG); > 721 tegra_qspi_writel(tqspi, ((rx_dma_phys >> 32) & 0xff), 722 QSPI_DMA_HI_ADDRESS_REG); 723 } 724 } 725 726 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1); 727 728 tqspi->is_curr_dma_xfer = true; 729 tqspi->dma_control_reg = val; 730 val |= QSPI_DMA_EN; 731 tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL); 732 733 return ret; 734 } 735 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH V1 6/6] spi: tegra210-quad: Introduce native DMA support 2025-01-03 6:04 ` [PATCH V1 6/6] spi: tegra210-quad: Introduce native DMA support Vishwaroop A 2025-01-03 14:21 ` kernel test robot 2025-01-03 23:16 ` kernel test robot @ 2025-01-06 13:04 ` Mark Brown 2 siblings, 0 replies; 5+ messages in thread From: Mark Brown @ 2025-01-06 13:04 UTC (permalink / raw) To: Vishwaroop A Cc: thierry.reding, jonathanh, skomatineni, ldewangan, linux-spi, linux-tegra, linux-kernel, kyarlagadda, smangipudi [-- Attachment #1: Type: text/plain, Size: 202 bytes --] On Fri, Jan 03, 2025 at 06:04:07AM +0000, Vishwaroop A wrote: > Change-Id: Icf3ef4767947cef67821c092ecd9ea6bccb2a4e4 Please don't include internal only things like change IDs in upstream submissions. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-01-06 13:04 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-01-04 21:00 [PATCH V1 6/6] spi: tegra210-quad: Introduce native DMA support kernel test robot -- strict thread matches above, loose matches on Subject: below -- 2025-01-03 6:04 [PATCH 0/6] Configure Clocks, Add Native Dma support Vishwaroop A 2025-01-03 6:04 ` [PATCH V1 6/6] spi: tegra210-quad: Introduce native DMA support Vishwaroop A 2025-01-03 14:21 ` kernel test robot 2025-01-03 23:16 ` kernel test robot 2025-01-06 13:04 ` Mark Brown
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