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From: "Michael S. Tsirkin" <mst@redhat.com>
To: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"jasowang@redhat.com" <jasowang@redhat.com>,
	"zhenzhong.duan@intel.com" <zhenzhong.duan@intel.com>,
	"kevin.tian@intel.com" <kevin.tian@intel.com>,
	"yi.l.liu@intel.com" <yi.l.liu@intel.com>,
	"joao.m.martins@oracle.com" <joao.m.martins@oracle.com>,
	"peterx@redhat.com" <peterx@redhat.com>,
	"tjeznach@rivosinc.com" <tjeznach@rivosinc.com>,
	"minwoo.im@samsung.com" <minwoo.im@samsung.com>
Subject: Re: [PATCH v1 15/19] memory: Add an API for ATS support
Date: Wed, 8 Jan 2025 13:10:57 -0500	[thread overview]
Message-ID: <20250108131034-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <20241129074332.87535-16-clement.mathieu--drif@eviden.com>

On Fri, Nov 29, 2024 at 07:44:00AM +0000, CLEMENT MATHIEU--DRIF wrote:
> From: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
> 
> IOMMU have to implement iommu_ats_request_translation to support ATS.
> 
> Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb
> entries returned by a translation request.
> 
> We decided not to use the existing translation operation for 2 reasons.
> First, ATS is designed to translate ranges and not isolated addresses.
> Second, we need ATS-specific parameters.
> 
> Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
> ---
>  include/exec/memory.h | 26 ++++++++++++++++++++++++++
>  system/memory.c       | 20 ++++++++++++++++++++
>  2 files changed, 46 insertions(+)
> 
> diff --git a/include/exec/memory.h b/include/exec/memory.h
> index c0d064dbd8..14166e2874 100644
> --- a/include/exec/memory.h
> +++ b/include/exec/memory.h
> @@ -148,6 +148,10 @@ struct IOMMUTLBEntry {
>      uint32_t         pasid;
>  };
>  
> +/* Check if an IOMMU TLB entry indicates a translation error */
> +#define IOMMU_TLB_ENTRY_TRANSLATION_ERROR(entry) ((((entry)->perm) & IOMMU_RW) \
> +                                                    == IOMMU_NONE)
> +
>  /*
>   * Bitmap for different IOMMUNotifier capabilities. Each notifier can
>   * register with one or multiple IOMMU Notifier capability bit(s).
> @@ -525,6 +529,20 @@ struct IOMMUMemoryRegionClass {
>       * @iommu: the IOMMUMemoryRegion
>       */
>      int (*num_indexes)(IOMMUMemoryRegion *iommu);
> +
> +    /**
> +     * @iommu_ats_request_translation:
> +     * This method must be implemented if the IOMMU has ATS enabled
> +     *
> +     * @see pci_ats_request_translation_pasid
> +     */
> +    ssize_t (*iommu_ats_request_translation)(IOMMUMemoryRegion *iommu,
> +                                             bool priv_req, bool exec_req,
> +                                             hwaddr addr, size_t length,
> +                                             bool no_write,
> +                                             IOMMUTLBEntry *result,
> +                                             size_t result_length,
> +                                             uint32_t *err_count);
>  };
>  
>  typedef struct RamDiscardListener RamDiscardListener;
> @@ -1883,6 +1901,14 @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n);
>  void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
>                                               IOMMUNotifier *n);
>  
> +ssize_t memory_region_iommu_ats_request_translation(IOMMUMemoryRegion *iommu_mr,
> +                                                bool priv_req, bool exec_req,
> +                                                hwaddr addr, size_t length,
> +                                                bool no_write,
> +                                                IOMMUTLBEntry *result,
> +                                                size_t result_length,
> +                                                uint32_t *err_count);
> +
>  /**
>   * memory_region_iommu_get_attr: return an IOMMU attr if get_attr() is
>   * defined on the IOMMU.
> diff --git a/system/memory.c b/system/memory.c
> index 85f6834cb3..7f6f3798e6 100644
> --- a/system/memory.c
> +++ b/system/memory.c
> @@ -2011,6 +2011,26 @@ void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
>      memory_region_update_iommu_notify_flags(iommu_mr, NULL);
>  }
>  
> +ssize_t memory_region_iommu_ats_request_translation(IOMMUMemoryRegion *iommu_mr,
> +                                                    bool priv_req,
> +                                                    bool exec_req,
> +                                                    hwaddr addr, size_t length,
> +                                                    bool no_write,
> +                                                    IOMMUTLBEntry *result,
> +                                                    size_t result_length,
> +                                                    uint32_t *err_count)
> +{
> +    IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
> +


line too long - just call the variable mr.

> +    if (!imrc->iommu_ats_request_translation) {
> +        return -ENODEV;
> +    }
> +
> +    return imrc->iommu_ats_request_translation(iommu_mr, priv_req, exec_req,
> +                                               addr, length, no_write, result,
> +                                               result_length, err_count);
> +}
> +
>  void memory_region_notify_iommu_one(IOMMUNotifier *notifier,
>                                      const IOMMUTLBEvent *event)
>  {
> -- 
> 2.47.0



  reply	other threads:[~2025-01-08 18:11 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-29  7:43 [PATCH v1 00/19] Rebase ATS onto lastest Qemu mailing list state CLEMENT MATHIEU--DRIF
2024-11-29  7:43 ` [PATCH v1 01/19] memory: Add permissions in IOMMUAccessFlags CLEMENT MATHIEU--DRIF
2024-11-29  7:43 ` [PATCH v1 02/19] intel_iommu: Declare supported PASID size CLEMENT MATHIEU--DRIF
2024-11-29  7:43 ` [PATCH v1 04/19] intel_iommu: Fill the PASID field when creating an IOMMUTLBEntry CLEMENT MATHIEU--DRIF
2024-12-23  5:50   ` Duan, Zhenzhong
2024-12-24  5:49     ` CLEMENT MATHIEU--DRIF
2024-11-29  7:43 ` [PATCH v1 03/19] memory: Allow to store the PASID in IOMMUTLBEntry CLEMENT MATHIEU--DRIF
2024-11-29  7:43 ` [PATCH v1 05/19] pcie: Add helper to declare PASID capability for a pcie device CLEMENT MATHIEU--DRIF
2024-11-29  7:43 ` [PATCH v1 06/19] pcie: Helper functions to check if PASID is enabled CLEMENT MATHIEU--DRIF
2024-11-29  7:43 ` [PATCH v1 07/19] pcie: Helper function to check if ATS " CLEMENT MATHIEU--DRIF
2024-11-29  7:43 ` [PATCH v1 08/19] pci: Cache the bus mastering status in the device CLEMENT MATHIEU--DRIF
2024-11-29  7:43 ` [PATCH v1 09/19] pci: Add IOMMU operations to get memory regions with PASID CLEMENT MATHIEU--DRIF
2024-11-29  7:43 ` [PATCH v1 10/19] intel_iommu: Implement the get_memory_region_pasid iommu operation CLEMENT MATHIEU--DRIF
2024-11-29  7:43 ` [PATCH v1 11/19] memory: Store user data pointer in the IOMMU notifiers CLEMENT MATHIEU--DRIF
2024-11-29  7:43 ` [PATCH v1 12/19] pci: Add a pci-level initialization function for iommu notifiers CLEMENT MATHIEU--DRIF
2024-11-29  7:43 ` [PATCH v1 13/19] atc: Generic ATC that can be used by PCIe devices that support SVM CLEMENT MATHIEU--DRIF
2024-11-29  7:43 ` [PATCH v1 14/19] atc: Add unit tests CLEMENT MATHIEU--DRIF
2024-11-29  7:44 ` [PATCH v1 15/19] memory: Add an API for ATS support CLEMENT MATHIEU--DRIF
2025-01-08 18:10   ` Michael S. Tsirkin [this message]
2025-01-09  6:10     ` CLEMENT MATHIEU--DRIF
2024-11-29  7:44 ` [PATCH v1 16/19] pci: Add a pci-level API for ATS CLEMENT MATHIEU--DRIF
2024-11-29  7:44 ` [PATCH v1 17/19] intel_iommu: Set address mask when a translation fails and adjust W permission CLEMENT MATHIEU--DRIF
2024-11-29  7:44 ` [PATCH v1 18/19] intel_iommu: Return page walk level even when the translation fails CLEMENT MATHIEU--DRIF
2024-11-29  7:44 ` [PATCH v1 19/19] intel_iommu: Add support for ATS CLEMENT MATHIEU--DRIF

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