From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2042.outbound.protection.outlook.com [40.107.244.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B1C620E320 for ; Fri, 10 Jan 2025 13:47:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.42 ARC-Seal:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736516857; cv=fail; b=WDgc2OjiU72zTgsV0NsgToQhQ+l6gH4DRZdBQdghl/zpuWzP1XO5rY+CxiiRE+bdW6/RTP0ElW1DoOGfag8Q8tFxniGOgKzlrDG4zQrhjKb/R9hsPxr9KqWh2bBXQLTzTmXIax53Kjy4oCX9Vmtnn7AqzZpEdx//J+EL5Mq4+4c= ARC-Message-Signature:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736516857; c=relaxed/simple; bh=SXV4ySd43w6B1vs9xsMvFAxYYuuWDtBKhERSr7uOONc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Yun3NgWii3pVvqpshHsP0Hiq3NtkzRMANB8zE5ddpseSWXmldTQlld4h2ejQFqQz9xQ/wFYWLVymw5cuVgTUCvnzvhUDjsjl5JYBX7HYJvK7A66cIuSZ1y0x+7k6p1mas0Yz4+9CMg6RdCXe90e1Wp+t3mu5cd3SO/3BBvaFs8g= ARC-Authentication-Results:i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=tOjh3ivY; arc=fail smtp.client-ip=40.107.244.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="tOjh3ivY" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=RQKgYV0/24oqAIzXtIt+WGL+qCOsewbe+WnyRlweGmQinf8MVBg1pDGbN2GtAcLwAw8sEpHYr4AL0VUXRyEYyg6fQpK8bWiRujzvc43H3SQelGGIocq2nA+MqYtW+o5aOV+IBV3NCSCdw4Zh5A9ZbJOpIkGgxZ1Q80rUFUjASMo9/vzkeZ/4ODCu7HUWny49J+3BlD/+0vFwAUxhX3usqbe+PCO5LJgqrl4p6QjyhN4IYUj9vLuUNKxecKsOjCEsfHUfu2/d9ppaRaXP8l6YDdIx8ZthDYu4Mkp7Zt1jHtIbrUib5vRQ3niq5fnMcN74eXPYF4sk0731ub++dNmV+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=UTZQ12FTnwZHwH81OXwZLiDeqrzqFbxv/eFpzR2o7Ew=; b=sQLeRZnEuCF4ECflJ4SHIDXA/HI5ANf1BaBcKQl+gNwNJ3OUrw2EDTTGA68TrnA0YtLJae5zxiACrHEH55Q6IniWXK0uXYflJJyMX9awCTH6+8rMThneqGCgC6TMIUVctp4Qhddh2D8Le+52C472UAcqm0UOFOjeQN/50TBmat4bFBX3HKD1GN3zGZRiIxJmAzQ/HzKExifgTWqW9VN9IOqR58SORoTAm4WZ4ubwbEkWxUmEeUTCM735+NOB5Os0beYU0k/rqfdQMWBz5QADN1k4/8Y+//aw0bU5eUTmwVOM7j1eUJLTtfTakpi76fYQcet16pL+fBhaq96feHX2yg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UTZQ12FTnwZHwH81OXwZLiDeqrzqFbxv/eFpzR2o7Ew=; b=tOjh3ivYbaCWGAH2c2GjsXcJVi1PsaiLW6cdzEp9DtUt0C6wTNiizigN0LH+iO6LwF8Gxa6LQUgGx8bHSLf9fQ7QM91L2y1ISgzFNLEP8CYGiiKA80JyoDMen8D7IFBStDvfi4dJ4h5SZUyxxZiIuPCL2yI9/MSeQM5wU4G+3aTtkzsV7MzNNN+gKTAge3lcRDY3mTEjxx9FLU0wDvVrujluFgp2F7xsVfyY2W34L3AI0KyLNAu95LxZ2IA+shRf0Z6G8CL5ovlWAjzNJDJY7wMcqjaFnN3xMyGkKzJEt6cHZlYnn3O55eBiYNzjgBPPXwaPt7A+EQL/QP78teWsmw== Received: from SJ0PR13CA0216.namprd13.prod.outlook.com (2603:10b6:a03:2c1::11) by SJ0PR12MB6735.namprd12.prod.outlook.com (2603:10b6:a03:479::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8335.11; Fri, 10 Jan 2025 13:47:31 +0000 Received: from SJ5PEPF00000203.namprd05.prod.outlook.com (2603:10b6:a03:2c1:cafe::bd) by SJ0PR13CA0216.outlook.office365.com (2603:10b6:a03:2c1::11) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8356.6 via Frontend Transport; Fri, 10 Jan 2025 13:47:31 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SJ5PEPF00000203.mail.protection.outlook.com (10.167.244.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8335.7 via Frontend Transport; Fri, 10 Jan 2025 13:47:31 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 10 Jan 2025 05:47:26 -0800 Received: from r-build-bsp-02.mtr.labs.mlnx (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 10 Jan 2025 05:47:25 -0800 From: Vadim Pasternak To: , CC: , Vadim Pasternak Subject: [PATCH platform-next 08/11] platform: mellanox: mlx-platform: Add support for new Nvidia system Date: Fri, 10 Jan 2025 15:45:06 +0200 Message-ID: <20250110134515.8164-9-vadimp@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20250110134515.8164-1-vadimp@nvidia.com> References: <20250110134515.8164-1-vadimp@nvidia.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000203:EE_|SJ0PR12MB6735:EE_ X-MS-Office365-Filtering-Correlation-Id: 1040d4d9-a383-4bce-30c8-08dd317d54b2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?pD50f2FCJarvYwU/LUrksO435OrW9KPR/PZOSe4RrW4ctw5oSXjAMSshmVEN?= =?us-ascii?Q?TsCQX72KTsEQMIxI4TkBhSACFTFzVrLEQ1pYNjX8WZnNebpa0IB6KyD32iqC?= =?us-ascii?Q?dTaNFvC+R4LHnHpaICWiUgLrTLeRWuWg2Z0QoEYBK/caXfcm1+PCaBII0If4?= =?us-ascii?Q?GtAQsQam+d3RWedmwu2jptStXe1Gf0lh0pQksZ0fr28ZXtCCHSUztKmQkP3H?= =?us-ascii?Q?BJ4Ys2Za2nZHCFWJB7HrmpU8ezf/ZsE4E833pQB3JcZAnVoOnEVY/yzWMXHn?= =?us-ascii?Q?Z1AI5mccWdnB6gcURAKKVKsUj24C7lWAc4hhQx9aVb4xiBrJ2AfXpg2VhXyX?= =?us-ascii?Q?cqvIfH1j5P5qOPJCGdW0rHokIad4YjKAxWDAZQ/k9O/owyoflwKtkupHgIQx?= =?us-ascii?Q?QQd2KmiO4fa2/2uiQicZoamdhHPZYDyfMXTjlhTi0ow1kzo8rMU/riFNHGTV?= =?us-ascii?Q?3J0vib7IFeKl4wqYGjDyFjrvyvIu1IQvgi50cesUFADdTCBwWxWELmAwVf65?= =?us-ascii?Q?jt+Ors6nsgnTcykc7FJ9BeqHRUgJE/tkW1konHw1rl0TZaWSDB5rzJPNgIe7?= =?us-ascii?Q?GEJvHFDtNEFZOn2wD11cmJUVFoVoyZREgL06/7zn9fb5GXjGhACc/KW66ah3?= =?us-ascii?Q?HnXu+70gr2povhgwlp8kd5UxU+teqTjuS+QgsJ7FUzlwVJ8wfnBRtiFnvcXd?= =?us-ascii?Q?rcfAwD3NHYwfJgCM8bySzBr/huHc1d3iTpY+1eBdDNpGzIRFCEYQuyp628rc?= =?us-ascii?Q?J0eqw/4tA5UQzO0UtTlvf3XkKVj5qN6v8WPyNzaN3YsVOCLVDY1TZlJc5BYi?= =?us-ascii?Q?RLzc2Kod+X5If8oLCBqTNkvh8E4ImLpuMeGu5VrHlatLNuFeL3MGf8gAKk5R?= =?us-ascii?Q?1Tp0+Y29vJF6imdJvodwPh6QaX4kzC/GKzyAdC1q4/3xXkYwXJzWyIcTOfTA?= =?us-ascii?Q?RnpYL0lq8CzMWLVWaPupRNEPaQSnf8jJU3tXBkURCZLyktsMjLheDLge3bvj?= =?us-ascii?Q?OoPeQjpWBqOP7pV0MqKwRr+JgWqix/T8UY0BnSE5zvqWNphcHTy5yTHW0BLE?= =?us-ascii?Q?49izxlBJ7KPXqzpFM2gpRo3D+gngLcA9/qX6F0fN9jCqwYOvymRBiFetLg77?= =?us-ascii?Q?zxlWiSxpKWpA9RHF6/HrysZrlFivGfBQ/JLudeY6PVVKc4TQla0c28Z2sLYS?= =?us-ascii?Q?Lx3Kwznl6x4xjYvB6xHgvpdbuoMPehrl/UU8ife+7g3J8cD0Tfj7vpI4BMWK?= =?us-ascii?Q?S4Sw7O1teBEtLDLGIoQh7EIFkAhpgJpwboDRi2hjNOZsNPOBrtZPOEBEELmf?= =?us-ascii?Q?YimGpo1lfNRJwY3/6BJza9Ey/ZdCeGqSFD2KL3RP6zWxtaT0bE4Ly/ah9yFH?= =?us-ascii?Q?QsBcgPZ5ocwBZvW9286whQLnpjnXWCQE9bJo7VshdcyGuTUSQUUlMwxQmE3M?= =?us-ascii?Q?xhbLJQgV3pTXiM0l3XWbm1Ej8hHlchISmBdDBnQOjgpbjMo2zOOfUw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jan 2025 13:47:31.6865 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1040d4d9-a383-4bce-30c8-08dd317d54b2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000203.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6735 Add support for SN5640 Nvidia switch. SN5640 is a 51.2Tbps switch based on Nvidia SPC-5 ASIC. It provides up-to 400Gbps full bidirectional bandwidth per port. The system supports 64 OSFP cages and fits into standard 2U racks. SN5640 Features: - 64 OSFP ports supporting 2.5Gbps - 400Gbps speeds. - Air-cooled with 4 + 1 redundant fan units. - 2 + 2 redundant 2000W PSUs. - System management board based on AMD CPU with secure-boot support. Signed-off-by: Vadim Pasternak Reviewed-by: Oleksandr Shamray --- drivers/platform/mellanox/mlx-platform.c | 95 ++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c index ebb90d42a583..378875926810 100644 --- a/drivers/platform/mellanox/mlx-platform.c +++ b/drivers/platform/mellanox/mlx-platform.c @@ -3042,6 +3042,60 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = { .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT, }; +/* Platform hotplug for next-generation 800G systems family data */ +static struct mlxreg_core_item mlxplat_mlxcpld_ng800_hi171_items[] = { + { + .data = mlxplat_mlxcpld_ext_psu_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, + .mask = MLXPLAT_CPLD_PSU_EXT_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), + .inversed = 1, + .health = false, + }, + { + .data = mlxplat_mlxcpld_modular_pwr_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, + .mask = MLXPLAT_CPLD_PWR_EXT_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), + .inversed = 0, + .health = false, + }, + { + .data = mlxplat_mlxcpld_xdr_fan_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + .mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .capability_mask = MLXPLAT_CPLD_FAN_CAP_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_items_data), + .inversed = 1, + .health = false, + }, + { + .data = mlxplat_mlxcpld_default_asic_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, + .mask = MLXPLAT_CPLD_ASIC_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), + .inversed = 0, + .health = true, + }, +}; + +static +struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_hi171_data = { + .items = mlxplat_mlxcpld_ng800_hi171_items, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_ng800_hi171_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, + .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, +}; + /* Platform led default data */ static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { { @@ -4528,6 +4582,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { .mask = GENMASK(7, 0) & ~BIT(4), .mode = 0644, }, + { + .label = "shutdown_unlock", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0644, + }, { .label = "erot1_ap_reset", .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, @@ -7353,6 +7413,27 @@ static int __init mlxplat_dmi_smart_switch_matched(const struct dmi_system_id *d return mlxplat_register_platform_device(); } +static int __init mlxplat_dmi_ng400_hi171_matched(const struct dmi_system_id *dmi) +{ + int i; + + mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; + mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data); + mlxplat_mux_data = mlxplat_ng800_mux_data; + mlxplat_hotplug = &mlxplat_mlxcpld_ng800_hi171_data; + mlxplat_hotplug->deferred_nr = + mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; + mlxplat_led = &mlxplat_default_ng_led_data; + mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; + mlxplat_fan = &mlxplat_xdr_fan_data; + for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) + mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type3[i]; + mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; + mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; + + return mlxplat_register_platform_device(); +} + static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { { .callback = mlxplat_dmi_default_wc_matched, @@ -7453,6 +7534,20 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { DMI_MATCH(DMI_BOARD_NAME, "VMOD0019"), }, }, + { + .callback = mlxplat_dmi_ng400_hi171_matched, + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "VMOD0022"), + DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI171"), + }, + }, + { + .callback = mlxplat_dmi_ng400_hi171_matched, + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "VMOD0022"), + DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI172"), + }, + }, { .callback = mlxplat_dmi_msn274x_matched, .matches = { -- 2.44.0