Re: [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

On Fri, 10 Jan 2025 11:55:50 +0000
<shiju.jose@huawei.com> wrote:

> From: Shiju Jose <shiju.jose@huawei.com>
> 
> Add updates in the CXL events records and CXL trace events implementations
> for the changes in CXL spec rev 3.1.
> 
> Shiju Jose (6):
>   cxl/events: Update Common Event Record to CXL spec rev 3.1
>   cxl/events: Add Component Identifier formatting for CXL spec rev 3.1
>   cxl/events: Update General Media Event Record to CXL spec rev 3.1
>   cxl/events: Update DRAM Event Record to CXL spec rev 3.1
>   cxl/events: Update Memory Module Event Record to CXL spec rev 3.1
>   cxl/test: Update test code for event records to CXL spec rev 3.1
> 
> Changes:
> V4 -> V5
> 1. Reverted changes made in v4 for overcoming parsing error when
> libtraceevent in userspace parses the CXL trace events, for rasdaemon.
> This was due to trace event's format file is larger than PAGE_SIZE, not
> supported reading complete format file in one go in the kernel and thus
> fixed in the rasdaemon.

Great to see that resolved.

> 2. Rebased to v6.13-rc5.

Should probably say why when doing a rebase to something other than rc1.
In this case this is what cxl.git/next is based on after some fixes earlier
in the cycle so a sensible choice for this set.

As far as I'm concerned this set is ready to go, but more eyes always good
if anyone has time! Same for the ras-daemon series once this is queued for
the kernel.

Jonathan

> 3. Tested with rasdaemon and ras-mc-ctl tools updated for CXL spec rev 3.1
>    event record changes.