From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Samuel Tardieu" <sam@rfc1149.net>,
qemu-arm@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
"Felipe Balbi" <balbi@kernel.org>,
"Subbaraya Sundeep" <sundeep.lkml@gmail.com>,
"Alistair Francis" <alistair@alistair23.me>,
"Joel Stanley" <joel@jms.id.au>,
"Alexandre Iooss" <erdnaxe@crans.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 2/3] hw/arm/stellaris: Add 'armv7m' local variable
Date: Sun, 12 Jan 2025 23:56:13 +0100 [thread overview]
Message-ID: <20250112225614.33723-3-philmd@linaro.org> (raw)
In-Reply-To: <20250112225614.33723-1-philmd@linaro.org>
While the TYPE_ARMV7M object forward its NVIC interrupt lines,
it is somehow misleading to name it 'nvic'. Add the 'armv7m'
local variable for clarity, but also keep the 'nvic' variable
behaving like before when used for wiring IRQ lines.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/stellaris.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 1bba96df14e..7303e096ef7 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1031,7 +1031,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
*/
Object *soc_container;
- DeviceState *gpio_dev[7], *nvic;
+ DeviceState *gpio_dev[7], *armv7m, *nvic;
qemu_irq gpio_in[7][8];
qemu_irq gpio_out[7][8];
qemu_irq adc;
@@ -1095,19 +1095,20 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4);
sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
- nvic = qdev_new(TYPE_ARMV7M);
- object_property_add_child(soc_container, "v7m", OBJECT(nvic));
- qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
- qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
- qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
- qdev_prop_set_bit(nvic, "enable-bitband", true);
- qdev_connect_clock_in(nvic, "cpuclk",
+ armv7m = qdev_new(TYPE_ARMV7M);
+ object_property_add_child(soc_container, "v7m", OBJECT(armv7m));
+ qdev_prop_set_uint32(armv7m, "num-irq", NUM_IRQ_LINES);
+ qdev_prop_set_uint8(armv7m, "num-prio-bits", NUM_PRIO_BITS);
+ qdev_prop_set_string(armv7m, "cpu-type", ms->cpu_type);
+ qdev_prop_set_bit(armv7m, "enable-bitband", true);
+ qdev_connect_clock_in(armv7m, "cpuclk",
qdev_get_clock_out(ssys_dev, "SYSCLK"));
/* This SoC does not connect the systick reference clock */
- object_property_set_link(OBJECT(nvic), "memory",
+ object_property_set_link(OBJECT(armv7m), "memory",
OBJECT(get_system_memory()), &error_abort);
/* This will exit with an error if the user passed us a bad cpu_type */
- sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(armv7m), &error_fatal);
+ nvic = armv7m;
/* Now we can wire up the IRQ and MMIO of the system registers */
sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000);
--
2.47.1
next prev parent reply other threads:[~2025-01-12 22:57 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-12 22:56 [PATCH 0/3] hw/arm/v7m: Remove Cortex-M &first_cpu uses Philippe Mathieu-Daudé
2025-01-12 22:56 ` [PATCH 1/3] hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m' Philippe Mathieu-Daudé
2025-01-12 23:39 ` Alistair Francis
2025-01-12 22:56 ` Philippe Mathieu-Daudé [this message]
2025-01-12 22:58 ` [PATCH 2/3] hw/arm/stellaris: Add 'armv7m' local variable Philippe Mathieu-Daudé
2025-01-12 23:42 ` Alistair Francis
2025-01-12 22:56 ` [PATCH 3/3] hw/arm/v7m: Remove use of &first_cpu in machine_init() Philippe Mathieu-Daudé
2025-01-12 23:46 ` Alistair Francis
2025-01-13 8:27 ` Samuel Tardieu
2025-01-27 12:58 ` [PATCH 0/3] hw/arm/v7m: Remove Cortex-M &first_cpu uses Peter Maydell
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