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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-437c7499821sm27124325e9.2.2025.01.15.07.39.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2025 07:39:27 -0800 (PST) Date: Wed, 15 Jan 2025 16:39:27 +0100 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH v3 6/6] target/riscv: add RVA23S64 profile Message-ID: <20250115-28bfced9dc48ff95a89a6f0c@orel> References: <20250115134957.2179085-1-dbarboza@ventanamicro.com> <20250115134957.2179085-7-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250115134957.2179085-7-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Wed, Jan 15, 2025 at 10:49:57AM -0300, Daniel Henrique Barboza wrote: > Add RVA23S64 as described in [1]. This profile inherits all mandatory > extensions of RVA23U64 and RVA22S64, making it a child of both profiles. > > A new "rva23s64" profile CPU is also added. This is the generated > riscv,isa for it (taken via -M dumpdtb): > > rv64imafdcbvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ > ziccrse_zicond_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_ > zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_ > zkt_zvbb_zve32f_zve32x_zve64f_zve64d_zve64x_zvfhmin_zvkb_zvkt_shcounterenw_ > sha_shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_smnpm_smstateen_ssccptr_ > sscofpmf_sscounterenw_ssnpm_ssstateen_sstc_sstvala_sstvecd_ssu64xl_ > supm_svade_svinval_svnapot_svpbmt > > [1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu-qom.h | 1 + > target/riscv/cpu.c | 39 +++++++++++++++++++++++++++++++++++++++ > 2 files changed, 40 insertions(+) > > diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h > index 53ead481a9..4cfdb74891 100644 > --- a/target/riscv/cpu-qom.h > +++ b/target/riscv/cpu-qom.h > @@ -41,6 +41,7 @@ > #define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64") > #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64") > #define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64") > +#define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64") > #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") > #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") > #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 761da41e53..50e65932f6 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -2421,10 +2421,41 @@ static RISCVCPUProfile RVA23U64 = { > } > }; > > +/* > + * As with RVA23U64, RVA23S64 also defines 'named features'. > + * > + * Cache related features that we consider enabled since we don't > + * implement cache: Ssccptr > + * > + * Other named features that we already implement: Sstvecd, Sstvala, > + * Sscounterenw, Ssu64xl > + * > + * The remaining features/extensions comes from RVA23U64. ^ RVA23S64 > + */ > +static RISCVCPUProfile RVA23S64 = { > + .u_parent = &RVA23U64, > + .s_parent = &RVA22S64, > + .name = "rva23s64", > + .misa_ext = RVS, > + .priv_spec = PRIV_VERSION_1_13_0, > + .satp_mode = VM_1_10_SV39, > + .ext_offsets = { > + /* New in RVA23S64 */ > + CPU_CFG_OFFSET(ext_svnapot), CPU_CFG_OFFSET(ext_sstc), > + CPU_CFG_OFFSET(ext_sscofpmf), CPU_CFG_OFFSET(ext_ssnpm), > + > + /* Named features: Sha */ > + CPU_CFG_OFFSET(ext_sha), > + > + RISCV_PROFILE_EXT_LIST_END > + } > +}; > + > RISCVCPUProfile *riscv_profiles[] = { > &RVA22U64, > &RVA22S64, > &RVA23U64, > + &RVA23S64, > NULL, > }; > > @@ -2918,6 +2949,13 @@ static void rva23u64_profile_cpu_init(Object *obj) > > RVA23U64.enabled = true; > } > + > +static void rva23s64_profile_cpu_init(Object *obj) > +{ > + rv64i_bare_cpu_init(obj); > + > + RVA23S64.enabled = true; > +} > #endif > > static const gchar *riscv_gdb_arch_name(CPUState *cs) > @@ -3198,6 +3236,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init), > DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init), > DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, MXL_RV64, rva23u64_profile_cpu_init), > + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23S64, MXL_RV64, rva23s64_profile_cpu_init), > #endif /* TARGET_RISCV64 */ > }; > > -- > 2.47.1 > Otherwise, Reviewed-by: Andrew Jones