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([191.202.238.10]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3f0379eff69sm4952177b6e.41.2025.01.15.05.50.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2025 05:50:06 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 0/6] target/riscv: RVA23 profile support Date: Wed, 15 Jan 2025 10:49:51 -0300 Message-ID: <20250115134957.2179085-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.47.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::244; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x244.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Hi, In this new version we're now implementing u-mode and s-mode profile dependencies, as suggested by Drew in v2. This makes implementing s-mode profiles easier since those profiles usually inherits from both their equivalent u-mode profiles and from a previous s-mode profile. This is done in patch 3. Patch 4 is a change made to prevent a warning that will occur after patch 6, where we're adding RVA23S64 by making it dependent on both RVA23U64 and RVA22S64. Patches based on alistair/riscv-to-apply.next. Changes from v2: - patch 3 (new): - add u_parent and s_parent attributes in RISCVCPUProfile - patch 4 (new): - do not issue warnings when a profile runs in a newer priv_ver - patch 6 (former 4): - add RVA22S64 as the s_parent of RVA23S64. Declare RVA23S64 by listing just its own exclusive extensions - v2 link: https://lore.kernel.org/qemu-riscv/20250114190001.1650942-1-dbarboza@ventanamicro.com/ Daniel Henrique Barboza (6): target/riscv: add ssu64xl target/riscv: use RVB in RVA22U64 target/riscv: add profile u_parent and s_parent target/riscv: change priv_ver check in validate_profile() target/riscv: add RVA23U64 profile target/riscv: add RVA23S64 profile target/riscv/cpu-qom.h | 2 + target/riscv/cpu.c | 81 ++++++++++++++++++++++++++++-- target/riscv/cpu.h | 3 +- target/riscv/tcg/tcg-cpu.c | 37 ++++++++++---- tests/data/acpi/riscv64/virt/RHCT | Bin 390 -> 400 bytes 5 files changed, 109 insertions(+), 14 deletions(-) -- 2.47.1