From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F7E51DFD8 for ; Sun, 19 Jan 2025 12:24:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.41 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737289445; cv=none; b=bf+NTW58CgId6tounCwobop3EgFoSXI6wFfdpL6rW6i0Isi1k1GUWhzLX/U8Y1aTn6ybgfwk+uIzjDTAXviFNbqT7MX63Oz50GjPH7ixLRgyC/5JYdCQ9V5lJTYUncav+10VqOxBTjxlfgHoJCbroYRVcmGQm83JfNDBhWMWt1I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737289445; c=relaxed/simple; bh=w13kqS+lBbIiBPGX8yjRSvHt+GUTvV8lmLkerMXfa0Y=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=u8B+nf57YJRRewO66Kvq2XLZlfis0idlurncNTZBkWiJhcb36ZwP2s1KhUfER2lgj4kt2XGBmgma12FhEkdIgy+KVfftxbpz9Wq8pmzncehI4v3Hqxlfm0n3jIwxNS6OK0ViuFM3/GyagvxafHjgxv/XUr6ljk4D/B7IwI3/aaE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=CzVjT1la; arc=none smtp.client-ip=209.85.216.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="CzVjT1la" Received: by mail-pj1-f41.google.com with SMTP id 98e67ed59e1d1-2f42992f608so4994166a91.0 for ; Sun, 19 Jan 2025 04:24:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737289443; x=1737894243; darn=vger.kernel.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=ZZSuDJrfL4csxPwdTtRVca8OzgYxjKHdWPdCI/f9wuc=; b=CzVjT1la6HN9Go+ayPBfTxgtvK2SnX8gjj9xMp3HdqRVjCyRq45mVNSoxAHfVD71+g Wmn/yFl5eRZ6pQyJRYnncgZ2USm1h+4UcfeRaqO3T+VGsqwB1Nt+uQxBDDLLBHPbCQAF iiNNNuOwyhPKNdEzZAj30hWu6RDLBLUjLDWVqlrPo0J7qrCmKcTF0B2lksylaU5Hj6DZ E1Bqh95+9gM/vV4H5q3fUsNsPIJ12NiIIwFg7DUjF8B1Oadbgl9azpxY6e1VlTtt4U1C giUoRCJfOuZ0hIcKFVCbFCfAVrG/fq2EftHV7rK3HuzTQz4Kr1QE+OvNCizdJ0LFcuPa CWYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737289443; x=1737894243; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ZZSuDJrfL4csxPwdTtRVca8OzgYxjKHdWPdCI/f9wuc=; b=mf3djobWE6fgvnZKXnLOYcEt4RQ2GhFNXqyb0U9Fpey2M2WmQcd+3az6CVMYh+oMsj uxW019YWbhuVD89iOVr7R4/80tOWk5fwgv/zxFMD7TC90tBfZ1KiNYa+40vx/u2VFis/ ddqheoZrw7X3Yj2fX/WaBTBro/5gU6j/gDhvx1v4u6SmQ1djNWRQtmkLUIhFKW2itEe0 gzXdL/LIpiwd0PbAhtR1O5JxNIlqNuA53V5JM8FVQhZuWcbRd4ZGbtQhwSC4qN5xAaZG lNXeB+wXifvmPHnE40bLemxXuEQuwpZ4fhbYpYlcafLeUNgw7SpyFaHKDda2p968AqJn 3GTQ== X-Forwarded-Encrypted: i=1; AJvYcCWlPkDMAgXjHz7kY4S57yxmWiDBFSfA/XhFmDLfZrIe3RWtkxGA31M9f4QaIu5wAa9FM1hWTPMMf1Q=@vger.kernel.org X-Gm-Message-State: AOJu0YzcFamYhY8nXWY++PkYNsZSxBE0QRTKjhDKDJBSzWiEX4eewNDb 3995SS6oi7donupDPhDjzZQg2uLYMSS93YGKQWvVbCxthUdfe9sW2EDF5PKeJw== X-Gm-Gg: ASbGnctuKOGhUZKJec77q4FFV54kcXEQfIvgC36sDGlM3Dk2G2keZNZWBiyWSdc2MoG aPJ48h4csJxWEQ42tlW/fHpFGAnyslQjtVtFwb+6KsC90ZISOjrrPzRi8ZZPheTx0eFuGn1OCHQ RxwZowdnFI1uyRkH7rJuQOVxpow19WHaLsomHL20x0+PQdD4M0MYdc4/SVMcC2inhhlTyWzLFq+ XPZtlUgF9W4aguv+4gVDGCEQb5m3/w6O2BZckhQewpFNE0eG4p4kAZa1BedDGIrTq6iEjxaXTne oCUBNw== X-Google-Smtp-Source: AGHT+IFaNI/U2vzipJAr5YyNs2IN3u2D5+L74EF9nC37A9IjbU+RcZd6uAYCl4fwMzd8lJfalGvyUA== X-Received: by 2002:a17:90b:534b:b0:2f6:f107:fae6 with SMTP id 98e67ed59e1d1-2f782d32397mr11435071a91.23.1737289443232; Sun, 19 Jan 2025 04:24:03 -0800 (PST) Received: from thinkpad ([120.56.195.253]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f77619ed33sm5563566a91.23.2025.01.19.04.23.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jan 2025 04:24:02 -0800 (PST) Date: Sun, 19 Jan 2025 17:53:53 +0530 From: Manivannan Sadhasivam To: Chen Wang Cc: kw@linux.com, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, bhelgaas@google.com, unicorn_wang@outlook.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, lee@kernel.org, lpieralisi@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, pbrobinson@gmail.com, robh@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com, helgaas@kernel.org Subject: Re: [PATCH v3 2/5] PCI: sg2042: Add Sophgo SG2042 PCIe driver Message-ID: <20250119122353.v3tzitthmu5tu3dg@thinkpad> References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Wed, Jan 15, 2025 at 03:06:57PM +0800, Chen Wang wrote: > From: Chen Wang > > Add support for PCIe controller in SG2042 SoC. The controller > uses the Cadence PCIe core programmed by pcie-cadence*.c. The > PCIe controller will work in host mode only. > Please add more info about the IP. Like IP revision, PCIe Gen, lane count, etc... > Signed-off-by: Chen Wang > --- > drivers/pci/controller/cadence/Kconfig | 13 + > drivers/pci/controller/cadence/Makefile | 1 + > drivers/pci/controller/cadence/pcie-sg2042.c | 528 +++++++++++++++++++ > 3 files changed, 542 insertions(+) > create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c > > diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig > index 8a0044bb3989..292eb2b20e9c 100644 > --- a/drivers/pci/controller/cadence/Kconfig > +++ b/drivers/pci/controller/cadence/Kconfig > @@ -42,6 +42,18 @@ config PCIE_CADENCE_PLAT_EP > endpoint mode. This PCIe controller may be embedded into many > different vendors SoCs. > > +config PCIE_SG2042 > + bool "Sophgo SG2042 PCIe controller (host mode)" > + depends on ARCH_SOPHGO || COMPILE_TEST > + depends on OF > + select IRQ_MSI_LIB > + select PCI_MSI > + select PCIE_CADENCE_HOST > + help > + Say Y here if you want to support the Sophgo SG2042 PCIe platform > + controller in host mode. Sophgo SG2042 PCIe controller uses Cadence > + PCIe core. > + > config PCI_J721E > bool > > @@ -67,4 +79,5 @@ config PCI_J721E_EP > Say Y here if you want to support the TI J721E PCIe platform > controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe > core. > + Spurious newline. > endmenu > diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile > index 9bac5fb2f13d..4df4456d9539 100644 > --- a/drivers/pci/controller/cadence/Makefile > +++ b/drivers/pci/controller/cadence/Makefile > @@ -4,3 +4,4 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o > obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o > obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o > obj-$(CONFIG_PCI_J721E) += pci-j721e.o > +obj-$(CONFIG_PCIE_SG2042) += pcie-sg2042.o > diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c > new file mode 100644 > index 000000000000..56797c2af755 > --- /dev/null > +++ b/drivers/pci/controller/cadence/pcie-sg2042.c > @@ -0,0 +1,528 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * pcie-sg2042 - PCIe controller driver for Sophgo SG2042 SoC > + * > + * Copyright (C) 2024 Sophgo Technology Inc. > + * Copyright (C) 2024 Chen Wang > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "../../../irqchip/irq-msi-lib.h" > + > +#include "pcie-cadence.h" > + > +/* > + * SG2042 PCIe controller supports two ways to report MSI: > + * > + * - Method A, the PCIe controller implements an MSI interrupt controller > + * inside, and connect to PLIC upward through one interrupt line. > + * Provides memory-mapped MSI address, and by programming the upper 32 > + * bits of the address to zero, it can be compatible with old PCIe devices > + * that only support 32-bit MSI address. > + * > + * - Method B, the PCIe controller connects to PLIC upward through an > + * independent MSI controller "sophgo,sg2042-msi" on the SOC. The MSI > + * controller provides multiple(up to 32) interrupt sources to PLIC. > + * Compared with the first method, the advantage is that the interrupt > + * source is expanded, but because for SG2042, the MSI address provided by > + * the MSI controller is fixed and only supports 64-bit address(> 2^32), > + * it is not compatible with old PCIe devices that only support 32-bit MSI > + * address. > + * > + * Method A & B can be configured in DTS, default is Method B. How to configure them? I can only see "sophgo,sg2042-msi" in the binding. > + */ > + > +#define MAX_MSI_IRQS 8 > +#define MAX_MSI_IRQS_PER_CTRL 1 > +#define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL) > +#define MSI_DEF_NUM_VECTORS MAX_MSI_IRQS > +#define BYTE_NUM_PER_MSI_VEC 4 > + > +#define REG_CLEAR 0x0804 > +#define REG_STATUS 0x0810 > +#define REG_LINK0_MSI_ADDR_SIZE 0x085C > +#define REG_LINK1_MSI_ADDR_SIZE 0x080C > +#define REG_LINK0_MSI_ADDR_LOW 0x0860 > +#define REG_LINK0_MSI_ADDR_HIGH 0x0864 > +#define REG_LINK1_MSI_ADDR_LOW 0x0868 > +#define REG_LINK1_MSI_ADDR_HIGH 0x086C > + > +#define REG_CLEAR_LINK0_BIT 2 > +#define REG_CLEAR_LINK1_BIT 3 > +#define REG_STATUS_LINK0_BIT 2 > +#define REG_STATUS_LINK1_BIT 3 > + > +#define REG_LINK0_MSI_ADDR_SIZE_MASK GENMASK(15, 0) > +#define REG_LINK1_MSI_ADDR_SIZE_MASK GENMASK(31, 16) > + > +struct sg2042_pcie { > + struct cdns_pcie *cdns_pcie; > + > + struct regmap *syscon; > + > + u32 link_id; > + > + struct irq_domain *msi_domain; > + > + int msi_irq; > + > + dma_addr_t msi_phys; > + void *msi_virt; > + > + u32 num_applied_vecs; /* used to speed up ISR */ > + Get rid of the newline between struct members, please. > + raw_spinlock_t msi_lock; > + DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); > +}; > + [...] > +static int sg2042_pcie_setup_msi(struct sg2042_pcie *pcie, > + struct device_node *msi_node) > +{ > + struct device *dev = pcie->cdns_pcie->dev; > + struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); > + struct irq_domain *parent_domain; > + int ret = 0; > + > + if (!of_property_read_bool(msi_node, "msi-controller")) > + return -ENODEV; > + > + ret = of_irq_get_byname(msi_node, "msi"); > + if (ret <= 0) { > + dev_err(dev, "%pOF: failed to get MSI irq\n", msi_node); > + return ret; > + } > + pcie->msi_irq = ret; > + > + irq_set_chained_handler_and_data(pcie->msi_irq, > + sg2042_pcie_msi_chained_isr, pcie); > + > + parent_domain = irq_domain_create_linear(fwnode, MSI_DEF_NUM_VECTORS, > + &sg2042_pcie_msi_domain_ops, pcie); > + if (!parent_domain) { > + dev_err(dev, "%pfw: Failed to create IRQ domain\n", fwnode); > + return -ENOMEM; > + } > + irq_domain_update_bus_token(parent_domain, DOMAIN_BUS_NEXUS); > + The MSI controller is wired to PLIC isn't it? If so, why can't you use hierarchial MSI domain implementation as like other controller drivers? > + parent_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT; > + parent_domain->msi_parent_ops = &sg2042_pcie_msi_parent_ops; > + > + pcie->msi_domain = parent_domain; > + > + ret = sg2042_pcie_init_msi_data(pcie); > + if (ret) { > + dev_err(dev, "Failed to initialize MSI data!\n"); > + return ret; > + } > + > + return 0; > +} > + > +static void sg2042_pcie_free_msi(struct sg2042_pcie *pcie) > +{ > + struct device *dev = pcie->cdns_pcie->dev; > + > + if (pcie->msi_irq) > + irq_set_chained_handler_and_data(pcie->msi_irq, NULL, NULL); > + > + if (pcie->msi_virt) > + dma_free_coherent(dev, BYTE_NUM_PER_MSI_VEC * MAX_MSI_IRQS, > + pcie->msi_virt, pcie->msi_phys); > +} > + > +/* > + * SG2042 only support 4-byte aligned access, so for the rootbus (i.e. to read > + * the Root Port itself, read32 is required. For non-rootbus (i.e. to read > + * the PCIe peripheral registers, supports 1/2/4 byte aligned access, so > + * directly using read should be fine. > + * > + * The same is true for write. > + */ > +static int sg2042_pcie_config_read(struct pci_bus *bus, unsigned int devfn, > + int where, int size, u32 *value) > +{ > + if (pci_is_root_bus(bus)) > + return pci_generic_config_read32(bus, devfn, where, size, > + value); > + > + return pci_generic_config_read(bus, devfn, where, size, value); > +} > + > +static int sg2042_pcie_config_write(struct pci_bus *bus, unsigned int devfn, > + int where, int size, u32 value) > +{ > + if (pci_is_root_bus(bus)) > + return pci_generic_config_write32(bus, devfn, where, size, > + value); > + > + return pci_generic_config_write(bus, devfn, where, size, value); > +} > + > +static struct pci_ops sg2042_pcie_host_ops = { > + .map_bus = cdns_pci_map_bus, > + .read = sg2042_pcie_config_read, > + .write = sg2042_pcie_config_write, > +}; > + > +/* Dummy ops which will be assigned to cdns_pcie.ops, which must be !NULL. */ Because cadence code driver doesn't check for !ops? Please fix it instead. And the fix is trivial. > +static const struct cdns_pcie_ops sg2042_cdns_pcie_ops = {}; > + > +static int sg2042_pcie_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct device_node *np = dev->of_node; > + struct pci_host_bridge *bridge; > + struct device_node *np_syscon; > + struct device_node *msi_node; > + struct cdns_pcie *cdns_pcie; > + struct sg2042_pcie *pcie; > + struct cdns_pcie_rc *rc; > + struct regmap *syscon; > + int ret; > + > + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); > + if (!pcie) > + return -ENOMEM; > + > + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); > + if (!bridge) { > + dev_err(dev, "Failed to alloc host bridge!\n"); Use dev_err_probe() throughout the probe function. > + return -ENOMEM; > + } > + > + bridge->ops = &sg2042_pcie_host_ops; > + > + rc = pci_host_bridge_priv(bridge); > + cdns_pcie = &rc->pcie; > + cdns_pcie->dev = dev; > + cdns_pcie->ops = &sg2042_cdns_pcie_ops; > + pcie->cdns_pcie = cdns_pcie; > + > + np_syscon = of_parse_phandle(np, "sophgo,syscon-pcie-ctrl", 0); > + if (!np_syscon) { > + dev_err(dev, "Failed to get syscon node\n"); > + return -ENOMEM; -ENODEV > + } > + syscon = syscon_node_to_regmap(np_syscon); You should drop the np reference count once you are done with it. > + if (IS_ERR(syscon)) { > + dev_err(dev, "Failed to get regmap for syscon\n"); > + return -ENOMEM; PTR_ERR(syscon) > + } > + pcie->syscon = syscon; > + > + if (of_property_read_u32(np, "sophgo,link-id", &pcie->link_id)) { > + dev_err(dev, "Unable to parse sophgo,link-id\n"); "Unable to parse \"sophgo,link-id\"\n" > + return -EINVAL; > + } > + > + platform_set_drvdata(pdev, pcie); > + > + pm_runtime_enable(dev); > + > + ret = pm_runtime_get_sync(dev); Use pm_runtime_resume_and_get(). > + if (ret < 0) { > + dev_err(dev, "pm_runtime_get_sync failed\n"); > + goto err_get_sync; > + } > + > + msi_node = of_parse_phandle(dev->of_node, "msi-parent", 0); > + if (!msi_node) { > + dev_err(dev, "Failed to get msi-parent!\n"); > + return -1; -ENODATA > + } > + > + if (of_device_is_compatible(msi_node, "sophgo,sg2042-pcie-msi")) { > + ret = sg2042_pcie_setup_msi(pcie, msi_node); Same as above. np leak here. - Mani -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A82ACC02183 for ; Sun, 19 Jan 2025 12:24:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6Yf/ICeYVBH36tQoak9nl8NEMAkiueRjzDxZRgCl+f8=; b=o/Hz/z73wIw0WA NLl9dBqqEjVMOZ3r148FP3v08qJilqHB/GfQ9phlf4sqx5vXu0FI3sFCfS+zxMWVVJmWts36pPZXg Lp3lFucevX9+n0xcUmGx2Q6TLzpy2cvGfINyLkDEkVzXo1TQOljZzFlpc/iAFVsw6RX2z+QRWctod zA6dre/02f3nzjn6oVSbrMDTlZvHern5YkZk5eMgYPflScUQ5o2VlPF9bT6py+bcwQyd8YaJ5YUrw TO/ApCoMZcqoORYB+5FNgA1MMoB5FSwAuB4B7ArMNzAYpfdXxIl3JQMUEK3gInYGhEC2Qytn09tFc lLxL+ST8AD0ukTXjfzwg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tZULX-00000003rtq-2O7a; Sun, 19 Jan 2025 12:24:07 +0000 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tZULU-00000003rt2-1GuL for linux-riscv@lists.infradead.org; Sun, 19 Jan 2025 12:24:05 +0000 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-2ee709715d9so4961694a91.3 for ; Sun, 19 Jan 2025 04:24:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737289443; x=1737894243; darn=lists.infradead.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=ZZSuDJrfL4csxPwdTtRVca8OzgYxjKHdWPdCI/f9wuc=; b=p51gKAlTHG0leAKF9qTNumYAHlVbi+MPl9NjjEbDWzB96MDRR9+1NEb27S0UIlMECf qmUOyB1tDLgVxmXypP/sRJJXxzCCKV64C+sxdVlHIltB4Q3BtQ/fBoN87CjBsyPW8sOp GhJOWnqooWCpojMW9abK0B/Dg6kO/SCfMEGYK8b9Vn82jOgSVqXcM+ZdT85E0nYGFNej hzRYqJ8g6KH6aR6CCTXBAfSXfWipHFOewRZRzag3r8vy6LwJelET8Ehs/zzAekB6hYl/ 0e3FweDXZgSf9VWmqw6dJFD26Gm1kZT08pNCGtSubK0zi4UHBsqriv1L8QEbFlIJVXG3 lUfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737289443; x=1737894243; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ZZSuDJrfL4csxPwdTtRVca8OzgYxjKHdWPdCI/f9wuc=; b=nr/VN7oY6xiVlysGC+IpHHUffFP30iXxlUmPuoObOhBd3+cwJlkMGSwc5T3V/d3R+f jq3zWTQFJa+D64qwUkbRD03/fQp4zXDf4ae4IfisbE7rsphUYi7Qflf6Ix/MRnhg7bRI NF+bnk2D3Ytvaxe0mRqR1cTlIoZP8/TCiU5jYlNRnHo8wKX7MRAaDO3phW/19ZkI0amB NTBl8XuttBsi6NbirK4EBdOO2AzVpxNkVoacWrWs2msXFK7REdtyqAPSkrcv34jbf1xS CAZgJumEfmNAGjtUmoxywwW3HL+SN9PNuVK6RJKATTkKHshYq/9L/IvruieZdT2fdetZ uAFQ== X-Forwarded-Encrypted: i=1; AJvYcCW+tLEU4NLho0GXl5/6plDQc6+8E/FAkV8WT0muWyRGDFzTTQppKZTQcqkFP6LDggeAQjL2WZY+isRMhQ==@lists.infradead.org X-Gm-Message-State: AOJu0YySja1iQO9uNto8RfDE/Sykl41gWb6H6G30H7drHcykuWsWFBQZ ZjwezJXfSnZNDDQgtJfP9zbR3+T1bzbSMje3EqbDuUfvzirpNa4bUxee4iUUuw== X-Gm-Gg: ASbGncvFOheiAB7yqfGWSljprMkgZ35DFMq8XPCf+lTGgAor4QcUy9BeWvG1m4JusBT IdzifIRb1r8h5rzDCdNCFTipMLzoJ4FWqbhzyimWxYwhDotQRspuXuHq042G/CuFaIX3rYSpDpL 3VMMQ6Lwk0lmf+WvG5tyCoE6X/ETEx98WaQo7njK5FWbGrWU0P6Yis0Kzq9VhKjrCVCkRBZyMD+ S9/uHWNROxDG6Ouk2kZdRLvpyj4d/ml73ORwzBDGgi9J2ou+0Zdyo8d0yZGJzOw1ZvVlMIlw3yn 7EOIYQ== X-Google-Smtp-Source: AGHT+IFaNI/U2vzipJAr5YyNs2IN3u2D5+L74EF9nC37A9IjbU+RcZd6uAYCl4fwMzd8lJfalGvyUA== X-Received: by 2002:a17:90b:534b:b0:2f6:f107:fae6 with SMTP id 98e67ed59e1d1-2f782d32397mr11435071a91.23.1737289443232; Sun, 19 Jan 2025 04:24:03 -0800 (PST) Received: from thinkpad ([120.56.195.253]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f77619ed33sm5563566a91.23.2025.01.19.04.23.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jan 2025 04:24:02 -0800 (PST) Date: Sun, 19 Jan 2025 17:53:53 +0530 From: Manivannan Sadhasivam To: Chen Wang Cc: kw@linux.com, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, bhelgaas@google.com, unicorn_wang@outlook.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, lee@kernel.org, lpieralisi@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, pbrobinson@gmail.com, robh@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com, helgaas@kernel.org Subject: Re: [PATCH v3 2/5] PCI: sg2042: Add Sophgo SG2042 PCIe driver Message-ID: <20250119122353.v3tzitthmu5tu3dg@thinkpad> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250119_042404_422703_AF7EC23C X-CRM114-Status: GOOD ( 39.43 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gV2VkLCBKYW4gMTUsIDIwMjUgYXQgMDM6MDY6NTdQTSArMDgwMCwgQ2hlbiBXYW5nIHdyb3Rl Ogo+IEZyb206IENoZW4gV2FuZyA8dW5pY29ybl93YW5nQG91dGxvb2suY29tPgo+IAo+IEFkZCBz dXBwb3J0IGZvciBQQ0llIGNvbnRyb2xsZXIgaW4gU0cyMDQyIFNvQy4gVGhlIGNvbnRyb2xsZXIK PiB1c2VzIHRoZSBDYWRlbmNlIFBDSWUgY29yZSBwcm9ncmFtbWVkIGJ5IHBjaWUtY2FkZW5jZSou Yy4gVGhlCj4gUENJZSBjb250cm9sbGVyIHdpbGwgd29yayBpbiBob3N0IG1vZGUgb25seS4KPiAK ClBsZWFzZSBhZGQgbW9yZSBpbmZvIGFib3V0IHRoZSBJUC4gTGlrZSBJUCByZXZpc2lvbiwgUENJ ZSBHZW4sIGxhbmUgY291bnQsCmV0Yy4uLgoKPiBTaWduZWQtb2ZmLWJ5OiBDaGVuIFdhbmcgPHVu aWNvcm5fd2FuZ0BvdXRsb29rLmNvbT4KPiAtLS0KPiAgZHJpdmVycy9wY2kvY29udHJvbGxlci9j YWRlbmNlL0tjb25maWcgICAgICAgfCAgMTMgKwo+ICBkcml2ZXJzL3BjaS9jb250cm9sbGVyL2Nh ZGVuY2UvTWFrZWZpbGUgICAgICB8ICAgMSArCj4gIGRyaXZlcnMvcGNpL2NvbnRyb2xsZXIvY2Fk ZW5jZS9wY2llLXNnMjA0Mi5jIHwgNTI4ICsrKysrKysrKysrKysrKysrKysKPiAgMyBmaWxlcyBj aGFuZ2VkLCA1NDIgaW5zZXJ0aW9ucygrKQo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9w Y2kvY29udHJvbGxlci9jYWRlbmNlL3BjaWUtc2cyMDQyLmMKPiAKPiBkaWZmIC0tZ2l0IGEvZHJp dmVycy9wY2kvY29udHJvbGxlci9jYWRlbmNlL0tjb25maWcgYi9kcml2ZXJzL3BjaS9jb250cm9s bGVyL2NhZGVuY2UvS2NvbmZpZwo+IGluZGV4IDhhMDA0NGJiMzk4OS4uMjkyZWIyYjIwZTljIDEw MDY0NAo+IC0tLSBhL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvY2FkZW5jZS9LY29uZmlnCj4gKysr IGIvZHJpdmVycy9wY2kvY29udHJvbGxlci9jYWRlbmNlL0tjb25maWcKPiBAQCAtNDIsNiArNDIs MTggQEAgY29uZmlnIFBDSUVfQ0FERU5DRV9QTEFUX0VQCj4gIAkgIGVuZHBvaW50IG1vZGUuIFRo aXMgUENJZSBjb250cm9sbGVyIG1heSBiZSBlbWJlZGRlZCBpbnRvIG1hbnkKPiAgCSAgZGlmZmVy ZW50IHZlbmRvcnMgU29Dcy4KPiAgCj4gK2NvbmZpZyBQQ0lFX1NHMjA0Mgo+ICsJYm9vbCAiU29w aGdvIFNHMjA0MiBQQ0llIGNvbnRyb2xsZXIgKGhvc3QgbW9kZSkiCj4gKwlkZXBlbmRzIG9uIEFS Q0hfU09QSEdPIHx8IENPTVBJTEVfVEVTVAo+ICsJZGVwZW5kcyBvbiBPRgo+ICsJc2VsZWN0IElS UV9NU0lfTElCCj4gKwlzZWxlY3QgUENJX01TSQo+ICsJc2VsZWN0IFBDSUVfQ0FERU5DRV9IT1NU Cj4gKwloZWxwCj4gKwkgIFNheSBZIGhlcmUgaWYgeW91IHdhbnQgdG8gc3VwcG9ydCB0aGUgU29w aGdvIFNHMjA0MiBQQ0llIHBsYXRmb3JtCj4gKwkgIGNvbnRyb2xsZXIgaW4gaG9zdCBtb2RlLiBT b3BoZ28gU0cyMDQyIFBDSWUgY29udHJvbGxlciB1c2VzIENhZGVuY2UKPiArCSAgUENJZSBjb3Jl Lgo+ICsKPiAgY29uZmlnIFBDSV9KNzIxRQo+ICAJYm9vbAo+ICAKPiBAQCAtNjcsNCArNzksNSBA QCBjb25maWcgUENJX0o3MjFFX0VQCj4gIAkgIFNheSBZIGhlcmUgaWYgeW91IHdhbnQgdG8gc3Vw cG9ydCB0aGUgVEkgSjcyMUUgUENJZSBwbGF0Zm9ybQo+ICAJICBjb250cm9sbGVyIGluIGVuZHBv aW50IG1vZGUuIFRJIEo3MjFFIFBDSWUgY29udHJvbGxlciB1c2VzIENhZGVuY2UgUENJZQo+ICAJ ICBjb3JlLgo+ICsKClNwdXJpb3VzIG5ld2xpbmUuCgo+ICBlbmRtZW51Cj4gZGlmZiAtLWdpdCBh L2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvY2FkZW5jZS9NYWtlZmlsZSBiL2RyaXZlcnMvcGNpL2Nv bnRyb2xsZXIvY2FkZW5jZS9NYWtlZmlsZQo+IGluZGV4IDliYWM1ZmIyZjEzZC4uNGRmNDQ1NmQ5 NTM5IDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvY2FkZW5jZS9NYWtlZmls ZQo+ICsrKyBiL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvY2FkZW5jZS9NYWtlZmlsZQo+IEBAIC00 LDMgKzQsNCBAQCBvYmotJChDT05GSUdfUENJRV9DQURFTkNFX0hPU1QpICs9IHBjaWUtY2FkZW5j ZS1ob3N0Lm8KPiAgb2JqLSQoQ09ORklHX1BDSUVfQ0FERU5DRV9FUCkgKz0gcGNpZS1jYWRlbmNl LWVwLm8KPiAgb2JqLSQoQ09ORklHX1BDSUVfQ0FERU5DRV9QTEFUKSArPSBwY2llLWNhZGVuY2Ut cGxhdC5vCj4gIG9iai0kKENPTkZJR19QQ0lfSjcyMUUpICs9IHBjaS1qNzIxZS5vCj4gK29iai0k KENPTkZJR19QQ0lFX1NHMjA0MikgKz0gcGNpZS1zZzIwNDIubwo+IGRpZmYgLS1naXQgYS9kcml2 ZXJzL3BjaS9jb250cm9sbGVyL2NhZGVuY2UvcGNpZS1zZzIwNDIuYyBiL2RyaXZlcnMvcGNpL2Nv bnRyb2xsZXIvY2FkZW5jZS9wY2llLXNnMjA0Mi5jCj4gbmV3IGZpbGUgbW9kZSAxMDA2NDQKPiBp bmRleCAwMDAwMDAwMDAwMDAuLjU2Nzk3YzJhZjc1NQo+IC0tLSAvZGV2L251bGwKPiArKysgYi9k cml2ZXJzL3BjaS9jb250cm9sbGVyL2NhZGVuY2UvcGNpZS1zZzIwNDIuYwo+IEBAIC0wLDAgKzEs NTI4IEBACj4gKy8vIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiBHUEwtMi4wCj4gKy8qCj4gKyAq IHBjaWUtc2cyMDQyIC0gUENJZSBjb250cm9sbGVyIGRyaXZlciBmb3IgU29waGdvIFNHMjA0MiBT b0MKPiArICoKPiArICogQ29weXJpZ2h0IChDKSAyMDI0IFNvcGhnbyBUZWNobm9sb2d5IEluYy4K PiArICogQ29weXJpZ2h0IChDKSAyMDI0IENoZW4gV2FuZyA8dW5pY29ybl93YW5nQG91dGxvb2su Y29tPgo+ICsgKi8KPiArCj4gKyNpbmNsdWRlIDxsaW51eC9iaXRzLmg+Cj4gKyNpbmNsdWRlIDxs aW51eC9pcnEuaD4KPiArI2luY2x1ZGUgPGxpbnV4L2lycWNoaXAvY2hhaW5lZF9pcnEuaD4KPiAr I2luY2x1ZGUgPGxpbnV4L2lycWRvbWFpbi5oPgo+ICsjaW5jbHVkZSA8bGludXgva2VybmVsLmg+ Cj4gKyNpbmNsdWRlIDxsaW51eC9tZmQvc3lzY29uLmg+Cj4gKyNpbmNsdWRlIDxsaW51eC9tc2ku aD4KPiArI2luY2x1ZGUgPGxpbnV4L29mX2FkZHJlc3MuaD4KPiArI2luY2x1ZGUgPGxpbnV4L29m X2lycS5oPgo+ICsjaW5jbHVkZSA8bGludXgvb2ZfcGNpLmg+Cj4gKyNpbmNsdWRlIDxsaW51eC9w bGF0Zm9ybV9kZXZpY2UuaD4KPiArI2luY2x1ZGUgPGxpbnV4L3BtX3J1bnRpbWUuaD4KPiArI2lu Y2x1ZGUgPGxpbnV4L3JlZ21hcC5oPgo+ICsKPiArI2luY2x1ZGUgIi4uLy4uLy4uL2lycWNoaXAv aXJxLW1zaS1saWIuaCIKPiArCj4gKyNpbmNsdWRlICJwY2llLWNhZGVuY2UuaCIKPiArCj4gKy8q Cj4gKyAqIFNHMjA0MiBQQ0llIGNvbnRyb2xsZXIgc3VwcG9ydHMgdHdvIHdheXMgdG8gcmVwb3J0 IE1TSToKPiArICoKPiArICogLSBNZXRob2QgQSwgdGhlIFBDSWUgY29udHJvbGxlciBpbXBsZW1l bnRzIGFuIE1TSSBpbnRlcnJ1cHQgY29udHJvbGxlcgo+ICsgKiAgIGluc2lkZSwgYW5kIGNvbm5l Y3QgdG8gUExJQyB1cHdhcmQgdGhyb3VnaCBvbmUgaW50ZXJydXB0IGxpbmUuCj4gKyAqICAgUHJv dmlkZXMgbWVtb3J5LW1hcHBlZCBNU0kgYWRkcmVzcywgYW5kIGJ5IHByb2dyYW1taW5nIHRoZSB1 cHBlciAzMgo+ICsgKiAgIGJpdHMgb2YgdGhlIGFkZHJlc3MgdG8gemVybywgaXQgY2FuIGJlIGNv bXBhdGlibGUgd2l0aCBvbGQgUENJZSBkZXZpY2VzCj4gKyAqICAgdGhhdCBvbmx5IHN1cHBvcnQg MzItYml0IE1TSSBhZGRyZXNzLgo+ICsgKgo+ICsgKiAtIE1ldGhvZCBCLCB0aGUgUENJZSBjb250 cm9sbGVyIGNvbm5lY3RzIHRvIFBMSUMgdXB3YXJkIHRocm91Z2ggYW4KPiArICogICBpbmRlcGVu ZGVudCBNU0kgY29udHJvbGxlciAic29waGdvLHNnMjA0Mi1tc2kiIG9uIHRoZSBTT0MuIFRoZSBN U0kKPiArICogICBjb250cm9sbGVyIHByb3ZpZGVzIG11bHRpcGxlKHVwIHRvIDMyKSBpbnRlcnJ1 cHQgc291cmNlcyB0byBQTElDLgo+ICsgKiAgIENvbXBhcmVkIHdpdGggdGhlIGZpcnN0IG1ldGhv ZCwgdGhlIGFkdmFudGFnZSBpcyB0aGF0IHRoZSBpbnRlcnJ1cHQKPiArICogICBzb3VyY2UgaXMg ZXhwYW5kZWQsIGJ1dCBiZWNhdXNlIGZvciBTRzIwNDIsIHRoZSBNU0kgYWRkcmVzcyBwcm92aWRl ZCBieQo+ICsgKiAgIHRoZSBNU0kgY29udHJvbGxlciBpcyBmaXhlZCBhbmQgb25seSBzdXBwb3J0 cyA2NC1iaXQgYWRkcmVzcyg+IDJeMzIpLAo+ICsgKiAgIGl0IGlzIG5vdCBjb21wYXRpYmxlIHdp dGggb2xkIFBDSWUgZGV2aWNlcyB0aGF0IG9ubHkgc3VwcG9ydCAzMi1iaXQgTVNJCj4gKyAqICAg YWRkcmVzcy4KPiArICoKPiArICogTWV0aG9kIEEgJiBCIGNhbiBiZSBjb25maWd1cmVkIGluIERU UywgZGVmYXVsdCBpcyBNZXRob2QgQi4KCkhvdyB0byBjb25maWd1cmUgdGhlbT8gSSBjYW4gb25s eSBzZWUgInNvcGhnbyxzZzIwNDItbXNpIiBpbiB0aGUgYmluZGluZy4KCj4gKyAqLwo+ICsKPiAr I2RlZmluZSBNQVhfTVNJX0lSUVMJCTgKPiArI2RlZmluZSBNQVhfTVNJX0lSUVNfUEVSX0NUUkwJ MQo+ICsjZGVmaW5lIE1BWF9NU0lfQ1RSTFMJCShNQVhfTVNJX0lSUVMgLyBNQVhfTVNJX0lSUVNf UEVSX0NUUkwpCj4gKyNkZWZpbmUgTVNJX0RFRl9OVU1fVkVDVE9SUwlNQVhfTVNJX0lSUVMKPiAr I2RlZmluZSBCWVRFX05VTV9QRVJfTVNJX1ZFQwk0Cj4gKwo+ICsjZGVmaW5lIFJFR19DTEVBUgkJ MHgwODA0Cj4gKyNkZWZpbmUgUkVHX1NUQVRVUwkJMHgwODEwCj4gKyNkZWZpbmUgUkVHX0xJTksw X01TSV9BRERSX1NJWkUJMHgwODVDCj4gKyNkZWZpbmUgUkVHX0xJTksxX01TSV9BRERSX1NJWkUJ MHgwODBDCj4gKyNkZWZpbmUgUkVHX0xJTkswX01TSV9BRERSX0xPVwkweDA4NjAKPiArI2RlZmlu ZSBSRUdfTElOSzBfTVNJX0FERFJfSElHSAkweDA4NjQKPiArI2RlZmluZSBSRUdfTElOSzFfTVNJ X0FERFJfTE9XCTB4MDg2OAo+ICsjZGVmaW5lIFJFR19MSU5LMV9NU0lfQUREUl9ISUdICTB4MDg2 Qwo+ICsKPiArI2RlZmluZSBSRUdfQ0xFQVJfTElOSzBfQklUCTIKPiArI2RlZmluZSBSRUdfQ0xF QVJfTElOSzFfQklUCTMKPiArI2RlZmluZSBSRUdfU1RBVFVTX0xJTkswX0JJVAkyCj4gKyNkZWZp bmUgUkVHX1NUQVRVU19MSU5LMV9CSVQJMwo+ICsKPiArI2RlZmluZSBSRUdfTElOSzBfTVNJX0FE RFJfU0laRV9NQVNLCUdFTk1BU0soMTUsIDApCj4gKyNkZWZpbmUgUkVHX0xJTksxX01TSV9BRERS X1NJWkVfTUFTSwlHRU5NQVNLKDMxLCAxNikKPiArCj4gK3N0cnVjdCBzZzIwNDJfcGNpZSB7Cj4g KwlzdHJ1Y3QgY2Ruc19wY2llCSpjZG5zX3BjaWU7Cj4gKwo+ICsJc3RydWN0IHJlZ21hcAkJKnN5 c2NvbjsKPiArCj4gKwl1MzIJCQlsaW5rX2lkOwo+ICsKPiArCXN0cnVjdCBpcnFfZG9tYWluCSpt c2lfZG9tYWluOwo+ICsKPiArCWludAkJCW1zaV9pcnE7Cj4gKwo+ICsJZG1hX2FkZHJfdAkJbXNp X3BoeXM7Cj4gKwl2b2lkCQkJKm1zaV92aXJ0Owo+ICsKPiArCXUzMgkJCW51bV9hcHBsaWVkX3Zl Y3M7IC8qIHVzZWQgdG8gc3BlZWQgdXAgSVNSICovCj4gKwoKR2V0IHJpZCBvZiB0aGUgbmV3bGlu ZSBiZXR3ZWVuIHN0cnVjdCBtZW1iZXJzLCBwbGVhc2UuCgo+ICsJcmF3X3NwaW5sb2NrX3QJCW1z aV9sb2NrOwo+ICsJREVDTEFSRV9CSVRNQVAobXNpX2lycV9pbl91c2UsIE1BWF9NU0lfSVJRUyk7 Cj4gK307Cj4gKwoKWy4uLl0KCj4gK3N0YXRpYyBpbnQgc2cyMDQyX3BjaWVfc2V0dXBfbXNpKHN0 cnVjdCBzZzIwNDJfcGNpZSAqcGNpZSwKPiArCQkJCSBzdHJ1Y3QgZGV2aWNlX25vZGUgKm1zaV9u b2RlKQo+ICt7Cj4gKwlzdHJ1Y3QgZGV2aWNlICpkZXYgPSBwY2llLT5jZG5zX3BjaWUtPmRldjsK PiArCXN0cnVjdCBmd25vZGVfaGFuZGxlICpmd25vZGUgPSBvZl9ub2RlX3RvX2Z3bm9kZShkZXYt Pm9mX25vZGUpOwo+ICsJc3RydWN0IGlycV9kb21haW4gKnBhcmVudF9kb21haW47Cj4gKwlpbnQg cmV0ID0gMDsKPiArCj4gKwlpZiAoIW9mX3Byb3BlcnR5X3JlYWRfYm9vbChtc2lfbm9kZSwgIm1z aS1jb250cm9sbGVyIikpCj4gKwkJcmV0dXJuIC1FTk9ERVY7Cj4gKwo+ICsJcmV0ID0gb2ZfaXJx X2dldF9ieW5hbWUobXNpX25vZGUsICJtc2kiKTsKPiArCWlmIChyZXQgPD0gMCkgewo+ICsJCWRl dl9lcnIoZGV2LCAiJXBPRjogZmFpbGVkIHRvIGdldCBNU0kgaXJxXG4iLCBtc2lfbm9kZSk7Cj4g KwkJcmV0dXJuIHJldDsKPiArCX0KPiArCXBjaWUtPm1zaV9pcnEgPSByZXQ7Cj4gKwo+ICsJaXJx X3NldF9jaGFpbmVkX2hhbmRsZXJfYW5kX2RhdGEocGNpZS0+bXNpX2lycSwKPiArCQkJCQkgc2cy MDQyX3BjaWVfbXNpX2NoYWluZWRfaXNyLCBwY2llKTsKPiArCj4gKwlwYXJlbnRfZG9tYWluID0g aXJxX2RvbWFpbl9jcmVhdGVfbGluZWFyKGZ3bm9kZSwgTVNJX0RFRl9OVU1fVkVDVE9SUywKPiAr CQkJCQkJICZzZzIwNDJfcGNpZV9tc2lfZG9tYWluX29wcywgcGNpZSk7Cj4gKwlpZiAoIXBhcmVu dF9kb21haW4pIHsKPiArCQlkZXZfZXJyKGRldiwgIiVwZnc6IEZhaWxlZCB0byBjcmVhdGUgSVJR IGRvbWFpblxuIiwgZndub2RlKTsKPiArCQlyZXR1cm4gLUVOT01FTTsKPiArCX0KPiArCWlycV9k b21haW5fdXBkYXRlX2J1c190b2tlbihwYXJlbnRfZG9tYWluLCBET01BSU5fQlVTX05FWFVTKTsK PiArCgpUaGUgTVNJIGNvbnRyb2xsZXIgaXMgd2lyZWQgdG8gUExJQyBpc24ndCBpdD8gSWYgc28s IHdoeSBjYW4ndCB5b3UgdXNlCmhpZXJhcmNoaWFsIE1TSSBkb21haW4gaW1wbGVtZW50YXRpb24g YXMgbGlrZSBvdGhlciBjb250cm9sbGVyIGRyaXZlcnM/Cgo+ICsJcGFyZW50X2RvbWFpbi0+Zmxh Z3MgfD0gSVJRX0RPTUFJTl9GTEFHX01TSV9QQVJFTlQ7Cj4gKwlwYXJlbnRfZG9tYWluLT5tc2lf cGFyZW50X29wcyA9ICZzZzIwNDJfcGNpZV9tc2lfcGFyZW50X29wczsKPiArCj4gKwlwY2llLT5t c2lfZG9tYWluID0gcGFyZW50X2RvbWFpbjsKPiArCj4gKwlyZXQgPSBzZzIwNDJfcGNpZV9pbml0 X21zaV9kYXRhKHBjaWUpOwo+ICsJaWYgKHJldCkgewo+ICsJCWRldl9lcnIoZGV2LCAiRmFpbGVk IHRvIGluaXRpYWxpemUgTVNJIGRhdGEhXG4iKTsKPiArCQlyZXR1cm4gcmV0Owo+ICsJfQo+ICsK PiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9pZCBzZzIwNDJfcGNpZV9mcmVlX21z aShzdHJ1Y3Qgc2cyMDQyX3BjaWUgKnBjaWUpCj4gK3sKPiArCXN0cnVjdCBkZXZpY2UgKmRldiA9 IHBjaWUtPmNkbnNfcGNpZS0+ZGV2Owo+ICsKPiArCWlmIChwY2llLT5tc2lfaXJxKQo+ICsJCWly cV9zZXRfY2hhaW5lZF9oYW5kbGVyX2FuZF9kYXRhKHBjaWUtPm1zaV9pcnEsIE5VTEwsIE5VTEwp Owo+ICsKPiArCWlmIChwY2llLT5tc2lfdmlydCkKPiArCQlkbWFfZnJlZV9jb2hlcmVudChkZXYs IEJZVEVfTlVNX1BFUl9NU0lfVkVDICogTUFYX01TSV9JUlFTLAo+ICsJCQkJICBwY2llLT5tc2lf dmlydCwgcGNpZS0+bXNpX3BoeXMpOwo+ICt9Cj4gKwo+ICsvKgo+ICsgKiBTRzIwNDIgb25seSBz dXBwb3J0IDQtYnl0ZSBhbGlnbmVkIGFjY2Vzcywgc28gZm9yIHRoZSByb290YnVzIChpLmUuIHRv IHJlYWQKPiArICogdGhlIFJvb3QgUG9ydCBpdHNlbGYsIHJlYWQzMiBpcyByZXF1aXJlZC4gRm9y IG5vbi1yb290YnVzIChpLmUuIHRvIHJlYWQKPiArICogdGhlIFBDSWUgcGVyaXBoZXJhbCByZWdp c3RlcnMsIHN1cHBvcnRzIDEvMi80IGJ5dGUgYWxpZ25lZCBhY2Nlc3MsIHNvCj4gKyAqIGRpcmVj dGx5IHVzaW5nIHJlYWQgc2hvdWxkIGJlIGZpbmUuCj4gKyAqCj4gKyAqIFRoZSBzYW1lIGlzIHRy dWUgZm9yIHdyaXRlLgo+ICsgKi8KPiArc3RhdGljIGludCBzZzIwNDJfcGNpZV9jb25maWdfcmVh ZChzdHJ1Y3QgcGNpX2J1cyAqYnVzLCB1bnNpZ25lZCBpbnQgZGV2Zm4sCj4gKwkJCQkgICBpbnQg d2hlcmUsIGludCBzaXplLCB1MzIgKnZhbHVlKQo+ICt7Cj4gKwlpZiAocGNpX2lzX3Jvb3RfYnVz KGJ1cykpCj4gKwkJcmV0dXJuIHBjaV9nZW5lcmljX2NvbmZpZ19yZWFkMzIoYnVzLCBkZXZmbiwg d2hlcmUsIHNpemUsCj4gKwkJCQkJCSB2YWx1ZSk7Cj4gKwo+ICsJcmV0dXJuIHBjaV9nZW5lcmlj X2NvbmZpZ19yZWFkKGJ1cywgZGV2Zm4sIHdoZXJlLCBzaXplLCB2YWx1ZSk7Cj4gK30KPiArCj4g K3N0YXRpYyBpbnQgc2cyMDQyX3BjaWVfY29uZmlnX3dyaXRlKHN0cnVjdCBwY2lfYnVzICpidXMs IHVuc2lnbmVkIGludCBkZXZmbiwKPiArCQkJCSAgICBpbnQgd2hlcmUsIGludCBzaXplLCB1MzIg dmFsdWUpCj4gK3sKPiArCWlmIChwY2lfaXNfcm9vdF9idXMoYnVzKSkKPiArCQlyZXR1cm4gcGNp X2dlbmVyaWNfY29uZmlnX3dyaXRlMzIoYnVzLCBkZXZmbiwgd2hlcmUsIHNpemUsCj4gKwkJCQkJ CSAgdmFsdWUpOwo+ICsKPiArCXJldHVybiBwY2lfZ2VuZXJpY19jb25maWdfd3JpdGUoYnVzLCBk ZXZmbiwgd2hlcmUsIHNpemUsIHZhbHVlKTsKPiArfQo+ICsKPiArc3RhdGljIHN0cnVjdCBwY2lf b3BzIHNnMjA0Ml9wY2llX2hvc3Rfb3BzID0gewo+ICsJLm1hcF9idXMJPSBjZG5zX3BjaV9tYXBf YnVzLAo+ICsJLnJlYWQJCT0gc2cyMDQyX3BjaWVfY29uZmlnX3JlYWQsCj4gKwkud3JpdGUJCT0g c2cyMDQyX3BjaWVfY29uZmlnX3dyaXRlLAo+ICt9Owo+ICsKPiArLyogRHVtbXkgb3BzIHdoaWNo IHdpbGwgYmUgYXNzaWduZWQgdG8gY2Ruc19wY2llLm9wcywgd2hpY2ggbXVzdCBiZSAhTlVMTC4g Ki8KCkJlY2F1c2UgY2FkZW5jZSBjb2RlIGRyaXZlciBkb2Vzbid0IGNoZWNrIGZvciAhb3BzPyBQ bGVhc2UgZml4IGl0IGluc3RlYWQuIEFuZAp0aGUgZml4IGlzIHRyaXZpYWwuCgo+ICtzdGF0aWMg Y29uc3Qgc3RydWN0IGNkbnNfcGNpZV9vcHMgc2cyMDQyX2NkbnNfcGNpZV9vcHMgPSB7fTsKPiAr Cj4gK3N0YXRpYyBpbnQgc2cyMDQyX3BjaWVfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAq cGRldikKPiArewo+ICsJc3RydWN0IGRldmljZSAqZGV2ID0gJnBkZXYtPmRldjsKPiArCXN0cnVj dCBkZXZpY2Vfbm9kZSAqbnAgPSBkZXYtPm9mX25vZGU7Cj4gKwlzdHJ1Y3QgcGNpX2hvc3RfYnJp ZGdlICpicmlkZ2U7Cj4gKwlzdHJ1Y3QgZGV2aWNlX25vZGUgKm5wX3N5c2NvbjsKPiArCXN0cnVj dCBkZXZpY2Vfbm9kZSAqbXNpX25vZGU7Cj4gKwlzdHJ1Y3QgY2Ruc19wY2llICpjZG5zX3BjaWU7 Cj4gKwlzdHJ1Y3Qgc2cyMDQyX3BjaWUgKnBjaWU7Cj4gKwlzdHJ1Y3QgY2Ruc19wY2llX3JjICpy YzsKPiArCXN0cnVjdCByZWdtYXAgKnN5c2NvbjsKPiArCWludCByZXQ7Cj4gKwo+ICsJcGNpZSA9 IGRldm1fa3phbGxvYyhkZXYsIHNpemVvZigqcGNpZSksIEdGUF9LRVJORUwpOwo+ICsJaWYgKCFw Y2llKQo+ICsJCXJldHVybiAtRU5PTUVNOwo+ICsKPiArCWJyaWRnZSA9IGRldm1fcGNpX2FsbG9j X2hvc3RfYnJpZGdlKGRldiwgc2l6ZW9mKCpyYykpOwo+ICsJaWYgKCFicmlkZ2UpIHsKPiArCQlk ZXZfZXJyKGRldiwgIkZhaWxlZCB0byBhbGxvYyBob3N0IGJyaWRnZSFcbiIpOwoKVXNlIGRldl9l cnJfcHJvYmUoKSB0aHJvdWdob3V0IHRoZSBwcm9iZSBmdW5jdGlvbi4KCj4gKwkJcmV0dXJuIC1F Tk9NRU07Cj4gKwl9Cj4gKwo+ICsJYnJpZGdlLT5vcHMgPSAmc2cyMDQyX3BjaWVfaG9zdF9vcHM7 Cj4gKwo+ICsJcmMgPSBwY2lfaG9zdF9icmlkZ2VfcHJpdihicmlkZ2UpOwo+ICsJY2Ruc19wY2ll ID0gJnJjLT5wY2llOwo+ICsJY2Ruc19wY2llLT5kZXYgPSBkZXY7Cj4gKwljZG5zX3BjaWUtPm9w cyA9ICZzZzIwNDJfY2Ruc19wY2llX29wczsKPiArCXBjaWUtPmNkbnNfcGNpZSA9IGNkbnNfcGNp ZTsKPiArCj4gKwlucF9zeXNjb24gPSBvZl9wYXJzZV9waGFuZGxlKG5wLCAic29waGdvLHN5c2Nv bi1wY2llLWN0cmwiLCAwKTsKPiArCWlmICghbnBfc3lzY29uKSB7Cj4gKwkJZGV2X2VycihkZXYs ICJGYWlsZWQgdG8gZ2V0IHN5c2NvbiBub2RlXG4iKTsKPiArCQlyZXR1cm4gLUVOT01FTTsKCi1F Tk9ERVYKCj4gKwl9Cj4gKwlzeXNjb24gPSBzeXNjb25fbm9kZV90b19yZWdtYXAobnBfc3lzY29u KTsKCllvdSBzaG91bGQgZHJvcCB0aGUgbnAgcmVmZXJlbmNlIGNvdW50IG9uY2UgeW91IGFyZSBk b25lIHdpdGggaXQuCgo+ICsJaWYgKElTX0VSUihzeXNjb24pKSB7Cj4gKwkJZGV2X2VycihkZXYs ICJGYWlsZWQgdG8gZ2V0IHJlZ21hcCBmb3Igc3lzY29uXG4iKTsKPiArCQlyZXR1cm4gLUVOT01F TTsKClBUUl9FUlIoc3lzY29uKQoKPiArCX0KPiArCXBjaWUtPnN5c2NvbiA9IHN5c2NvbjsKPiAr Cj4gKwlpZiAob2ZfcHJvcGVydHlfcmVhZF91MzIobnAsICJzb3BoZ28sbGluay1pZCIsICZwY2ll LT5saW5rX2lkKSkgewo+ICsJCWRldl9lcnIoZGV2LCAiVW5hYmxlIHRvIHBhcnNlIHNvcGhnbyxs aW5rLWlkXG4iKTsKCiJVbmFibGUgdG8gcGFyc2UgXCJzb3BoZ28sbGluay1pZFwiXG4iCgo+ICsJ CXJldHVybiAtRUlOVkFMOwo+ICsJfQo+ICsKPiArCXBsYXRmb3JtX3NldF9kcnZkYXRhKHBkZXYs IHBjaWUpOwo+ICsKPiArCXBtX3J1bnRpbWVfZW5hYmxlKGRldik7Cj4gKwo+ICsJcmV0ID0gcG1f cnVudGltZV9nZXRfc3luYyhkZXYpOwoKVXNlIHBtX3J1bnRpbWVfcmVzdW1lX2FuZF9nZXQoKS4K Cj4gKwlpZiAocmV0IDwgMCkgewo+ICsJCWRldl9lcnIoZGV2LCAicG1fcnVudGltZV9nZXRfc3lu YyBmYWlsZWRcbiIpOwo+ICsJCWdvdG8gZXJyX2dldF9zeW5jOwo+ICsJfQo+ICsKPiArCW1zaV9u b2RlID0gb2ZfcGFyc2VfcGhhbmRsZShkZXYtPm9mX25vZGUsICJtc2ktcGFyZW50IiwgMCk7Cj4g KwlpZiAoIW1zaV9ub2RlKSB7Cj4gKwkJZGV2X2VycihkZXYsICJGYWlsZWQgdG8gZ2V0IG1zaS1w YXJlbnQhXG4iKTsKPiArCQlyZXR1cm4gLTE7CgotRU5PREFUQQoKPiArCX0KPiArCj4gKwlpZiAo b2ZfZGV2aWNlX2lzX2NvbXBhdGlibGUobXNpX25vZGUsICJzb3BoZ28sc2cyMDQyLXBjaWUtbXNp IikpIHsKPiArCQlyZXQgPSBzZzIwNDJfcGNpZV9zZXR1cF9tc2kocGNpZSwgbXNpX25vZGUpOwoK U2FtZSBhcyBhYm92ZS4gbnAgbGVhayBoZXJlLgoKLSBNYW5pCgotLSAK4K6u4K6j4K6/4K614K6j 4K+N4K6j4K6p4K+NIOCumuCupOCuvuCumuCuv+CuteCuruCvjQoKX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtcmlzY3YgbWFpbGluZyBsaXN0Cmxp bnV4LXJpc2N2QGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcv bWFpbG1hbi9saXN0aW5mby9saW51eC1yaXNjdgo=