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From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "jasowang@redhat.com" <jasowang@redhat.com>,
	"zhenzhong.duan@intel.com" <zhenzhong.duan@intel.com>,
	"kevin.tian@intel.com" <kevin.tian@intel.com>,
	"yi.l.liu@intel.com" <yi.l.liu@intel.com>,
	"joao.m.martins@oracle.com" <joao.m.martins@oracle.com>,
	"peterx@redhat.com" <peterx@redhat.com>,
	"mst@redhat.com" <mst@redhat.com>,
	"tjeznach@rivosinc.com" <tjeznach@rivosinc.com>,
	"minwoo.im@samsung.com" <minwoo.im@samsung.com>,
	CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
Subject: [PATCH v2 01/19] memory: Add permissions in IOMMUAccessFlags
Date: Mon, 20 Jan 2025 17:41:37 +0000	[thread overview]
Message-ID: <20250120174033.308518-2-clement.mathieu--drif@eviden.com> (raw)
In-Reply-To: <20250120174033.308518-1-clement.mathieu--drif@eviden.com>

From: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com>

This will be necessary for devices implementing ATS.
We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to
IOMMU_ACCESS_FLAG to support more access flags.
IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility.

Here are the flags added (defined by the PCIe 5 specification) :
    - Execute Requested
    - Privileged Mode Requested
    - Global
    - Untranslated Only

IOMMU_ACCESS_FLAG sets the additional flags to 0

Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com>
---
 include/exec/memory.h | 23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index 3ee1901b52..56c3a3515e 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -110,15 +110,34 @@ struct MemoryRegionSection {
 
 typedef struct IOMMUTLBEntry IOMMUTLBEntry;
 
-/* See address_space_translate: bit 0 is read, bit 1 is write.  */
+/*
+ * See address_space_translate:
+ *      - bit 0 : read
+ *      - bit 1 : write
+ *      - bit 2 : exec
+ *      - bit 3 : priv
+ *      - bit 4 : global
+ *      - bit 5 : untranslated only
+ */
 typedef enum {
     IOMMU_NONE = 0,
     IOMMU_RO   = 1,
     IOMMU_WO   = 2,
     IOMMU_RW   = 3,
+    IOMMU_EXEC = 4,
+    IOMMU_PRIV = 8,
+    IOMMU_GLOBAL = 16,
+    IOMMU_UNTRANSLATED_ONLY = 32,
 } IOMMUAccessFlags;
 
-#define IOMMU_ACCESS_FLAG(r, w) (((r) ? IOMMU_RO : 0) | ((w) ? IOMMU_WO : 0))
+#define IOMMU_ACCESS_FLAG(r, w)     (((r) ? IOMMU_RO : 0) | \
+                                    ((w) ? IOMMU_WO : 0))
+#define IOMMU_ACCESS_FLAG_FULL(r, w, x, p, g, uo) \
+                                    (IOMMU_ACCESS_FLAG(r, w) | \
+                                    ((x) ? IOMMU_EXEC : 0) | \
+                                    ((p) ? IOMMU_PRIV : 0) | \
+                                    ((g) ? IOMMU_GLOBAL : 0) | \
+                                    ((uo) ? IOMMU_UNTRANSLATED_ONLY : 0))
 
 struct IOMMUTLBEntry {
     AddressSpace    *target_as;
-- 
2.47.1


  reply	other threads:[~2025-01-20 17:42 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-20 17:41 [PATCH v2 00/19] intel_iommu: Add ATS support CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` CLEMENT MATHIEU--DRIF [this message]
2025-01-20 17:41 ` [PATCH v2 02/19] intel_iommu: Declare supported PASID size CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` [PATCH v2 03/19] memory: Allow to store the PASID in IOMMUTLBEntry CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` [PATCH v2 04/19] intel_iommu: Fill the PASID field when creating an IOMMUTLBEntry CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` [PATCH v2 05/19] pcie: Add helper to declare PASID capability for a pcie device CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` [PATCH v2 06/19] pcie: Helper functions to check if PASID is enabled CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` [PATCH v2 07/19] pcie: Helper function to check if ATS " CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` [PATCH v2 08/19] pci: Cache the bus mastering status in the device CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` [PATCH v2 09/19] pci: Add IOMMU operations to get memory regions with PASID CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` [PATCH v2 10/19] intel_iommu: Implement the get_memory_region_pasid iommu operation CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` [PATCH v2 11/19] memory: Store user data pointer in the IOMMU notifiers CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` [PATCH v2 12/19] pci: Add a pci-level initialization function for iommu notifiers CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` [PATCH v2 13/19] atc: Generic ATC that can be used by PCIe devices that support SVM CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` [PATCH v2 15/19] memory: Add an API for ATS support CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` [PATCH v2 14/19] atc: Add unit tests CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` [PATCH v2 16/19] pci: Add a pci-level API for ATS CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` [PATCH v2 17/19] intel_iommu: Set address mask when a translation fails and adjust W permission CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` [PATCH v2 18/19] intel_iommu: Return page walk level even when the translation fails CLEMENT MATHIEU--DRIF
2025-01-20 17:41 ` [PATCH v2 19/19] intel_iommu: Add support for ATS CLEMENT MATHIEU--DRIF
2025-02-19  6:10 ` [PATCH v2 00/19] intel_iommu: Add ATS support CLEMENT MATHIEU--DRIF
2025-02-20 21:13 ` Michael S. Tsirkin
2025-02-21  7:54   ` CLEMENT MATHIEU--DRIF

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