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[77.183.181.102]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5db7364258csm6021077a12.1.2025.01.20.12.37.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2025 12:37:57 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alistair Francis , Peter Maydell , Jean-Christophe Dubois , qemu-arm@nongnu.org, Andrey Smirnov , "Edgar E. Iglesias" , Bernhard Beschow Subject: [PATCH 00/21] Add i.MX 8M Plus EVK machine Date: Mon, 20 Jan 2025 21:37:27 +0100 Message-ID: <20250120203748.4687-1-shentey@gmail.com> X-Mailer: git-send-email 2.48.1 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=shentey@gmail.com; helo=mail-ed1-x533.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FREEMAIL_REPLY=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: UOOiZdpb9YFD This series adds a new aarch64 machine to QEMU: i.MX 8M Plus EVK [1]. It al= lows=0D for running Linux distributions such as Buildroot=0D (freescale_imx8mpevk_defconfig) and Arch Linux [2] via direct kernel boot.= =0D U-Boot does not work yet. I plan to use this machine myself and I also want= to=0D make it available to a bigger audience, so I propose to add it to QEMU. My = goal=0D would be to have it added for 10.0.=0D =0D The series includes the unreviewed patches of [3] and is structured as foll= ows:=0D The first four patches fix some issues in device models reused by the new=0D machine. Patches 5-18 add the machine step by step which includes documenta= tion.=0D Patches 19 and 20 add some further device models that I'd like to use with = the=0D new machine. The last patch is a fix I created during debugging but I don't= rely=0D on it.=0D =0D I've based some code on existing one (see "Based on" in file headers) and I= 'm=0D unsure how to handle the licensing and attribution correctly -- advice welc= ome.=0D The TCA6416 emulation is taken from the Xilinx fork where it is used in som= e=0D cadence machines. Would the respective upstream maintainers be willing to=0D maintain the device model upstream instead?=0D =0D [1] https://www.nxp.com/design/design-center/development-boards-and-designs= /8MPLUSLPD4-EVK=0D [2] https://archlinuxarm.org/platforms/armv8/generic=0D [3] https://patchew.org/QEMU/20250111183711.2338-1-shentey@gmail.com/=0D =0D Supersedes: 20250111183711.2338-1-shentey@gmail.com=0D =0D Bernhard Beschow (21):=0D hw/char/imx_serial: Fix reset value of UFCR register=0D hw/char/imx_serial: Update all state before restarting ageing timer=0D hw/pci-host/designware: Expose MSI IRQ=0D hw/usb/hcd-dwc3: Align global registers size with Linux=0D hw/arm: Add i.MX 8M Plus EVK board=0D hw/arm/fsl-imx8mp: Implement clock tree=0D hw/arm/fsl-imx8mp: Add SNVS=0D hw/arm/fsl-imx8mp: Add USDHC storage controllers=0D hw/arm/fsl-imx8mp: Add PCIe support=0D hw/arm/fsl-imx8mp: Add GPIO controllers=0D hw/arm/fsl-imx8mp: Add I2C controllers=0D hw/arm/fsl-imx8mp: Add SPI controllers=0D hw/arm/fsl-imx8mp: Add watchdog support=0D hw/arm/fsl-imx8mp: Implement gneral purpose timers=0D hw/arm/fsl-imx8mp: Add Ethernet controller=0D hw/arm/fsl-imx8mp: Add USB support=0D hw/arm/fsl-imx8mp: Add boot ROM=0D hw/arm/fsl-imx8mp: Add on-chip RAM=0D hw/rtc: Add Ricoh RS5C372 RTC emulation=0D hw/i2c: Import TCA6416 emulation from Xilinx=0D hw/gpio/imx_gpio: Don't clear input GPIO values upon reset=0D =0D MAINTAINERS | 16 +=0D docs/system/arm/imx8mp-evk.rst | 84 ++++=0D docs/system/target-arm.rst | 1 +=0D include/hw/arm/fsl-imx6.h | 4 +-=0D include/hw/arm/fsl-imx7.h | 4 +-=0D include/hw/arm/fsl-imx8mp.h | 284 +++++++++++=0D include/hw/char/imx_serial.h | 2 +-=0D include/hw/misc/imx8mp_ccm.h | 97 ++++=0D include/hw/pci-host/designware.h | 1 +=0D include/hw/pci-host/fsl_imx8m_phy.h | 27 +=0D include/hw/timer/imx_gpt.h | 1 +=0D include/hw/usb/hcd-dwc3.h | 2 +-=0D hw/arm/fsl-imx6.c | 13 +-=0D hw/arm/fsl-imx7.c | 13 +-=0D hw/arm/fsl-imx8mp.c | 736 ++++++++++++++++++++++++++++=0D hw/arm/imx8mp-evk.c | 74 +++=0D hw/char/imx_serial.c | 7 +-=0D hw/gpio/imx_gpio.c | 1 -=0D hw/gpio/tca6416.c | 122 +++++=0D hw/misc/imx8mp_ccm.c | 315 ++++++++++++=0D hw/pci-host/designware.c | 7 +-=0D hw/pci-host/fsl_imx8m_phy.c | 88 ++++=0D hw/rtc/rs5c372.c | 227 +++++++++=0D hw/timer/imx_gpt.c | 25 +=0D hw/usb/hcd-dwc3.c | 5 +=0D hw/arm/Kconfig | 25 +=0D hw/arm/meson.build | 2 +=0D hw/gpio/Kconfig | 5 +=0D hw/gpio/meson.build | 1 +=0D hw/gpio/trace-events | 4 +=0D hw/misc/meson.build | 1 +=0D hw/pci-host/Kconfig | 3 +=0D hw/pci-host/meson.build | 1 +=0D hw/rtc/Kconfig | 5 +=0D hw/rtc/meson.build | 1 +=0D hw/rtc/trace-events | 4 +=0D pc-bios/imx8mp-boot.rom | Bin 0 -> 258048 bytes=0D pc-bios/meson.build | 1 +=0D 38 files changed, 2195 insertions(+), 14 deletions(-)=0D create mode 100644 docs/system/arm/imx8mp-evk.rst=0D create mode 100644 include/hw/arm/fsl-imx8mp.h=0D create mode 100644 include/hw/misc/imx8mp_ccm.h=0D create mode 100644 include/hw/pci-host/fsl_imx8m_phy.h=0D create mode 100644 hw/arm/fsl-imx8mp.c=0D create mode 100644 hw/arm/imx8mp-evk.c=0D create mode 100644 hw/gpio/tca6416.c=0D create mode 100644 hw/misc/imx8mp_ccm.c=0D create mode 100644 hw/pci-host/fsl_imx8m_phy.c=0D create mode 100644 hw/rtc/rs5c372.c=0D create mode 100644 pc-bios/imx8mp-boot.rom=0D =0D -- =0D 2.48.1=0D =0D