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From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Steven Lee" <steven_lee@aspeedtech.com>,
	"Troy Lee" <leetroy@gmail.com>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Joel Stanley" <joel@jms.id.au>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
	<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 13/18] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0
Date: Tue, 21 Jan 2025 15:04:19 +0800	[thread overview]
Message-ID: <20250121070424.2465942-14-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250121070424.2465942-1-jamin_lin@aspeedtech.com>

Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its IRQ
table and machine name.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/arm/aspeed.c         | 8 ++++----
 hw/arm/aspeed_ast27x0.c | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index ae0405c654..402d55c556 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1654,12 +1654,12 @@ static void ast2700_evb_i2c_init(AspeedMachineState *bmc)
                             TYPE_TMP105, 0x4d);
 }
 
-static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data)
+static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
 
-    mc->desc = "Aspeed AST2700 EVB (Cortex-A35)";
+    mc->desc = "Aspeed AST2700 A0 EVB (Cortex-A35)";
     amc->soc_name  = "ast2700-a0";
     amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
     amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
@@ -1795,9 +1795,9 @@ static const TypeInfo aspeed_machine_types[] = {
         .class_init     = aspeed_minibmc_machine_ast1030_evb_class_init,
 #ifdef TARGET_AARCH64
     }, {
-        .name          = MACHINE_TYPE_NAME("ast2700-evb"),
+        .name          = MACHINE_TYPE_NAME("ast2700a0-evb"),
         .parent        = TYPE_ASPEED_MACHINE,
-        .class_init    = aspeed_machine_ast2700_evb_class_init,
+        .class_init    = aspeed_machine_ast2700a0_evb_class_init,
 #endif
     }, {
         .name          = TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index a95fed30cf..b32c4fcc35 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -73,7 +73,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
 #define AST2700_MAX_IRQ 256
 
 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
-static const int aspeed_soc_ast2700_irqmap[] = {
+static const int aspeed_soc_ast2700a0_irqmap[] = {
     [ASPEED_DEV_UART0]     = 132,
     [ASPEED_DEV_UART1]     = 132,
     [ASPEED_DEV_UART2]     = 132,
@@ -794,7 +794,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("ast2700.io", 0x0, 0x4000000);
 }
 
-static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data)
+static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, void *data)
 {
     static const char * const valid_cpu_types[] = {
         ARM_CPU_TYPE_NAME("cortex-a35"),
@@ -817,7 +817,7 @@ static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data)
     sc->uarts_num    = 13;
     sc->num_cpus     = 4;
     sc->uarts_base   = ASPEED_DEV_UART0;
-    sc->irqmap       = aspeed_soc_ast2700_irqmap;
+    sc->irqmap       = aspeed_soc_ast2700a0_irqmap;
     sc->memmap       = aspeed_soc_ast2700_memmap;
     sc->get_irq      = aspeed_soc_ast2700_get_irq;
 }
@@ -832,7 +832,7 @@ static const TypeInfo aspeed_soc_ast27x0_types[] = {
         .name           = "ast2700-a0",
         .parent         = TYPE_ASPEED27X0_SOC,
         .instance_init  = aspeed_soc_ast2700_init,
-        .class_init     = aspeed_soc_ast2700_class_init,
+        .class_init     = aspeed_soc_ast2700a0_class_init,
     },
 };
 
-- 
2.34.1


  parent reply	other threads:[~2025-01-21  7:06 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-21  7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
2025-01-21  7:04 ` Jamin Lin via
2025-01-21  7:04 ` [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0 Jamin Lin via
2025-01-29 17:03   ` Cédric Le Goater
2025-01-30  3:22     ` Andrew Jeffery
2025-02-04  6:50       ` Jamin Lin
2025-02-04  7:34         ` Cédric Le Goater
2025-02-04  8:22           ` Jamin Lin
2025-02-04 10:26             ` Cédric Le Goater
2025-01-30  3:27   ` Andrew Jeffery
2025-01-21  7:04 ` [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops Jamin Lin via
2025-01-21  7:04   ` Jamin Lin via
2025-01-30  3:32   ` Andrew Jeffery
2025-02-04  7:00     ` Jamin Lin
2025-01-21  7:04 ` [PATCH v1 03/18] hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0 Jamin Lin via
2025-01-21  7:04   ` Jamin Lin via
2025-01-21  7:04 ` [PATCH v1 04/18] hw/intc/aspeed: Support setting different memory and register size Jamin Lin via
2025-01-21  7:04   ` Jamin Lin via
2025-01-21  7:04 ` [PATCH v1 05/18] hw/intc/aspeed: Introduce helper functions for enable and status registers Jamin Lin via
2025-01-21  7:04   ` Jamin Lin via
2025-01-21  7:04 ` [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address Jamin Lin via
2025-01-21  7:04   ` Jamin Lin via
2025-01-30  3:55   ` Andrew Jeffery
2025-02-04  9:45     ` Jamin Lin
2025-01-21  7:04 ` [PATCH v1 07/18] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication Jamin Lin via
2025-01-21  7:04 ` [PATCH v1 08/18] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling Jamin Lin via
2025-01-21  7:04 ` [PATCH v1 09/18] hw/intc/aspeed: Add ID to trace events for better debugging Jamin Lin via
2025-01-21  7:04 ` [PATCH v1 10/18] hw/intc/aspeed: Add Support for AST2700 INTC1 Controller Jamin Lin via
2025-01-21  7:04   ` Jamin Lin via
2025-01-21  7:04 ` [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions Jamin Lin via
2025-01-30  4:05   ` Andrew Jeffery
2025-02-04  7:23     ` Jamin Lin
2025-02-04  7:29       ` Cédric Le Goater
2025-01-21  7:04 ` [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 Jamin Lin via
2025-01-30  4:19   ` Andrew Jeffery
2025-02-04  9:43     ` Jamin Lin
2025-02-05  3:50       ` Andrew Jeffery
2025-02-05  7:12         ` Jamin Lin
2025-02-05 23:39           ` Andrew Jeffery
2025-02-06  4:55             ` Joel Stanley
2025-02-06  5:15               ` Jamin Lin
2025-02-06  7:17                 ` Cédric Le Goater
2025-02-06  7:22                   ` Jamin Lin
2025-02-06  7:22           ` Cédric Le Goater
2025-02-06  7:24             ` Jamin Lin
2025-01-21  7:04 ` Jamin Lin via [this message]
2025-01-21  7:04 ` [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support " Jamin Lin via
2025-01-30  4:22   ` Andrew Jeffery
2025-02-03  8:55     ` Jamin Lin
2025-01-21  7:04 ` [PATCH v1 15/18] hw/misc/aspeed_hace: Fix coding style Jamin Lin via
2025-01-21  7:04   ` Jamin Lin via
2025-01-21  7:04 ` [PATCH v1 16/18] hw/misc/aspeed_hace: Add AST2700 support Jamin Lin via
2025-01-21  7:04   ` Jamin Lin via
2025-01-30  4:30   ` Andrew Jeffery
2025-01-21  7:04 ` [PATCH v1 17/18] hw/arm/aspeed_ast27x0: Add HACE support for AST2700 Jamin Lin via
2025-01-30  4:32   ` Andrew Jeffery
2025-01-21  7:04 ` [PATCH v1 18/18] hw/misc/aspeed_hace: (DROP) Fix boot issue in the Crypto Manager Self Test(WORKAROUND) Jamin Lin via
2025-01-21  7:04   ` Jamin Lin via
2025-01-31  7:34 ` [PATCH v1 00/18] Support AST2700 A1 Cédric Le Goater
2025-02-04  8:05   ` Jamin Lin
2025-06-30 20:28   ` Cédric Le Goater
2025-07-02  1:57     ` Jamin Lin
2025-07-02  6:43       ` Cédric Le Goater
2025-07-03  7:43         ` Jamin Lin

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