From: Jamin Lin via <qemu-arm@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops
Date: Tue, 21 Jan 2025 15:04:08 +0800 [thread overview]
Message-ID: <20250121070424.2465942-3-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250121070424.2465942-1-jamin_lin@aspeedtech.com>
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC0 (CPU DIE).
To support the INTC1 (I/O DIE) model, introduces a new "reg_ops" class
attribute. This allows setting different memory region operations to support
different INTC models.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 5 ++++-
include/hw/intc/aspeed_intc.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index df4da759e1..628f69ea88 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -302,7 +302,7 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
int i;
- memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s,
+ memory_region_init_io(&s->iomem, OBJECT(s), aic->reg_ops, s,
TYPE_ASPEED_INTC ".regs", ASPEED_INTC_NR_REGS << 2);
sysbus_init_mmio(sbd, &s->iomem);
@@ -319,11 +319,14 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)
static void aspeed_intc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
dc->desc = "ASPEED INTC Controller";
dc->realize = aspeed_intc_realize;
device_class_set_legacy_reset(dc, aspeed_intc_reset);
dc->vmsd = NULL;
+
+ aic->reg_ops = &aspeed_intc_ops;
}
static const TypeInfo aspeed_intc_info = {
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 10718ed4a1..9a73661403 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -39,6 +39,7 @@ struct AspeedINTCClass {
uint32_t num_lines;
uint32_t num_ints;
+ const MemoryRegionOps *reg_ops;
};
#endif /* ASPEED_INTC_H */
--
2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops
Date: Tue, 21 Jan 2025 15:04:08 +0800 [thread overview]
Message-ID: <20250121070424.2465942-3-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250121070424.2465942-1-jamin_lin@aspeedtech.com>
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC0 (CPU DIE).
To support the INTC1 (I/O DIE) model, introduces a new "reg_ops" class
attribute. This allows setting different memory region operations to support
different INTC models.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 5 ++++-
include/hw/intc/aspeed_intc.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index df4da759e1..628f69ea88 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -302,7 +302,7 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
int i;
- memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s,
+ memory_region_init_io(&s->iomem, OBJECT(s), aic->reg_ops, s,
TYPE_ASPEED_INTC ".regs", ASPEED_INTC_NR_REGS << 2);
sysbus_init_mmio(sbd, &s->iomem);
@@ -319,11 +319,14 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)
static void aspeed_intc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
dc->desc = "ASPEED INTC Controller";
dc->realize = aspeed_intc_realize;
device_class_set_legacy_reset(dc, aspeed_intc_reset);
dc->vmsd = NULL;
+
+ aic->reg_ops = &aspeed_intc_ops;
}
static const TypeInfo aspeed_intc_info = {
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 10718ed4a1..9a73661403 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -39,6 +39,7 @@ struct AspeedINTCClass {
uint32_t num_lines;
uint32_t num_ints;
+ const MemoryRegionOps *reg_ops;
};
#endif /* ASPEED_INTC_H */
--
2.34.1
next prev parent reply other threads:[~2025-01-21 7:06 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
2025-01-21 7:04 ` Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0 Jamin Lin via
2025-01-29 17:03 ` Cédric Le Goater
2025-01-30 3:22 ` Andrew Jeffery
2025-02-04 6:50 ` Jamin Lin
2025-02-04 7:34 ` Cédric Le Goater
2025-02-04 8:22 ` Jamin Lin
2025-02-04 10:26 ` Cédric Le Goater
2025-01-30 3:27 ` Andrew Jeffery
2025-01-21 7:04 ` Jamin Lin via [this message]
2025-01-21 7:04 ` [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops Jamin Lin via
2025-01-30 3:32 ` Andrew Jeffery
2025-02-04 7:00 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 03/18] hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0 Jamin Lin via
2025-01-21 7:04 ` Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 04/18] hw/intc/aspeed: Support setting different memory and register size Jamin Lin via
2025-01-21 7:04 ` Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 05/18] hw/intc/aspeed: Introduce helper functions for enable and status registers Jamin Lin via
2025-01-21 7:04 ` Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address Jamin Lin via
2025-01-21 7:04 ` Jamin Lin via
2025-01-30 3:55 ` Andrew Jeffery
2025-02-04 9:45 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 07/18] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 08/18] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 09/18] hw/intc/aspeed: Add ID to trace events for better debugging Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 10/18] hw/intc/aspeed: Add Support for AST2700 INTC1 Controller Jamin Lin via
2025-01-21 7:04 ` Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions Jamin Lin via
2025-01-30 4:05 ` Andrew Jeffery
2025-02-04 7:23 ` Jamin Lin
2025-02-04 7:29 ` Cédric Le Goater
2025-01-21 7:04 ` [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 Jamin Lin via
2025-01-30 4:19 ` Andrew Jeffery
2025-02-04 9:43 ` Jamin Lin
2025-02-05 3:50 ` Andrew Jeffery
2025-02-05 7:12 ` Jamin Lin
2025-02-05 23:39 ` Andrew Jeffery
2025-02-06 4:55 ` Joel Stanley
2025-02-06 5:15 ` Jamin Lin
2025-02-06 7:17 ` Cédric Le Goater
2025-02-06 7:22 ` Jamin Lin
2025-02-06 7:22 ` Cédric Le Goater
2025-02-06 7:24 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 13/18] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1 Jamin Lin via
2025-01-30 4:22 ` Andrew Jeffery
2025-02-03 8:55 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 15/18] hw/misc/aspeed_hace: Fix coding style Jamin Lin via
2025-01-21 7:04 ` Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 16/18] hw/misc/aspeed_hace: Add AST2700 support Jamin Lin via
2025-01-21 7:04 ` Jamin Lin via
2025-01-30 4:30 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 17/18] hw/arm/aspeed_ast27x0: Add HACE support for AST2700 Jamin Lin via
2025-01-30 4:32 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 18/18] hw/misc/aspeed_hace: (DROP) Fix boot issue in the Crypto Manager Self Test(WORKAROUND) Jamin Lin via
2025-01-21 7:04 ` Jamin Lin via
2025-01-31 7:34 ` [PATCH v1 00/18] Support AST2700 A1 Cédric Le Goater
2025-02-04 8:05 ` Jamin Lin
2025-06-30 20:28 ` Cédric Le Goater
2025-07-02 1:57 ` Jamin Lin
2025-07-02 6:43 ` Cédric Le Goater
2025-07-03 7:43 ` Jamin Lin
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