From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, Dave Jiang <dave.jiang@intel.com>,
"Alejandro Lucero" <alucerop@amd.com>,
Ira Weiny <ira.weiny@intel.com>
Subject: Re: [PATCH v2 5/5] cxl: Kill enum cxl_decoder_mode
Date: Thu, 23 Jan 2025 16:51:03 +0000 [thread overview]
Message-ID: <20250123165103.00004379@huawei.com> (raw)
In-Reply-To: <173753637863.3849855.16067432468334597297.stgit@dwillia2-xfh.jf.intel.com>
On Wed, 22 Jan 2025 00:59:38 -0800
Dan Williams <dan.j.williams@intel.com> wrote:
> Now that the operational mode of DPA capacity (ram vs pmem... etc) is
> tracked in the partition, and no code paths have dependencies on the
> mode implying the partition index, the ambiguous 'enum cxl_decoder_mode'
> can be cleaned up, specifically this ambiguity on whether the operation
> mode implied anything about the partition order.
>
> Endpoint decoders simply reference their assigned partition where the
> operational mode can be retrieved as partition mode.
>
> With this in place PMEM can now be partition0 which happens today when
> the RAM capacity size is zero. Dynamic RAM can appear above PMEM when
> DCD arrives, etc. Code sequences that hard coded the "PMEM after RAM"
> assumption can now just iterate partitions and consult the partition
> mode after the fact.
>
> Cc: Dave Jiang <dave.jiang@intel.com>
> Cc: Alejandro Lucero <alucerop@amd.com>
> Cc: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
A few things inline.
Jonathan
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 591aeb26c9e1..bb478e7b12f6 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
>
> -int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled,
> - enum cxl_decoder_mode mode)
> +int cxl_dpa_set_part(struct cxl_endpoint_decoder *cxled,
> + enum cxl_partition_mode mode)
> {
> struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> struct cxl_dev_state *cxlds = cxlmd->cxlds;
> struct device *dev = &cxled->cxld.dev;
> -
> - switch (mode) {
> - case CXL_DECODER_RAM:
> - case CXL_DECODER_PMEM:
> - break;
> - default:
> - dev_dbg(dev, "unsupported mode: %d\n", mode);
> - return -EINVAL;
> - }
> + int part;
>
> guard(rwsem_write)(&cxl_dpa_rwsem);
> if (cxled->cxld.flags & CXL_DECODER_F_ENABLE)
> return -EBUSY;
>
> - /*
> - * Only allow modes that are supported by the current partition
> - * configuration
> - */
> - if (mode == CXL_DECODER_PMEM && !cxl_pmem_size(cxlds)) {
> - dev_dbg(dev, "no available pmem capacity\n");
> - return -ENXIO;
> + part = -1;
> + for (int i = 0; i < cxlds->nr_partitions; i++)
Similar to previous comment can use early loop exit and
part as the loop iteration variable short code and no magic i
appears.
> + if (cxlds->part[i].mode == mode) {
> + part = i;
> + break;
> + }
> +
> + if (part < 0) {
> + dev_dbg(dev, "unsupported mode: %d\n", mode);
> + return -EINVAL;
> }
> - if (mode == CXL_DECODER_RAM && !cxl_ram_size(cxlds)) {
> - dev_dbg(dev, "no available ram capacity\n");
> +
> + if (!resource_size(&cxlds->part[part].res)) {
> + dev_dbg(dev, "no available capacity for mode: %d\n", mode);
> return -ENXIO;
> }
>
> - cxled->mode = mode;
> + cxled->part = part;
> return 0;
> }
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 9f0f6fdbc841..83b985d2ba76 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
>
> static int poison_by_decoder(struct device *dev, void *arg)
> {
> struct cxl_poison_context *ctx = arg;
> struct cxl_endpoint_decoder *cxled;
> + enum cxl_partition_mode mode;
> + struct cxl_dev_state *cxlds;
> struct cxl_memdev *cxlmd;
> u64 offset, length;
> int rc = 0;
> @@ -2728,11 +2733,17 @@ static int poison_by_decoder(struct device *dev, void *arg)
> return rc;
>
> cxlmd = cxled_to_memdev(cxled);
> + cxlds = cxlmd->cxlds;
> + if (cxled->part < 0)
> + mode = CXL_PARTMODE_NONE;
Ah. Here is our mysterious none. Maybe add a comment on what
this means in practice. Race condition, actual hole, crazy decoder
someone (e.g bios) setup?
> + else
> + mode = cxlds->part[cxled->part].mode;
> +
> if (cxled->skip) {
> offset = cxled->dpa_res->start - cxled->skip;
> length = cxled->skip;
> rc = cxl_mem_get_poison(cxlmd, offset, length, NULL);
> - if (rc == -EFAULT && cxled->mode == CXL_DECODER_RAM)
> + if (rc == -EFAULT && mode == CXL_PARTMODE_RAM)
> rc = 0;
> if (rc)
> return rc;
> @@ -2741,7 +2752,7 @@ static int poison_by_decoder(struct device *dev, void *arg)
> offset = cxled->dpa_res->start;
> length = cxled->dpa_res->end - offset + 1;
> rc = cxl_mem_get_poison(cxlmd, offset, length, cxled->cxld.region);
> - if (rc == -EFAULT && cxled->mode == CXL_DECODER_RAM)
> + if (rc == -EFAULT && mode == CXL_PARTMODE_RAM)
> rc = 0;
> if (rc)
> return rc;
> @@ -2749,7 +2760,7 @@ static int poison_by_decoder(struct device *dev, void *arg)
> /* Iterate until commit_end is reached */
> if (cxled->cxld.id == ctx->port->commit_end) {
> ctx->offset = cxled->dpa_res->end + 1;
> - ctx->mode = cxled->mode;
> + ctx->part = cxled->part;
> return 1;
> }
>
> @@ -2762,7 +2773,8 @@ int cxl_get_poison_by_endpoint(struct cxl_port *port)
> int rc = 0;
>
> ctx = (struct cxl_poison_context) {
> - .port = port
> + .port = port,
> + .part = -1,
> };
>
> rc = device_for_each_child(&port->dev, &ctx, poison_by_decoder);
> @@ -3206,14 +3218,18 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
> {
> struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> struct cxl_port *port = cxlrd_to_port(cxlrd);
> + struct cxl_dev_state *cxlds = cxlmd->cxlds;
> struct range *hpa = &cxled->cxld.hpa_range;
> + int rc, part = READ_ONCE(cxled->part);
> struct cxl_region_params *p;
> struct cxl_region *cxlr;
> struct resource *res;
> - int rc;
> +
> + if (part < 0)
> + return ERR_PTR(-EBUSY);
>
> do {
> - cxlr = __create_region(cxlrd, cxled->mode,
> + cxlr = __create_region(cxlrd, cxlds->part[part].mode,
> atomic_read(&cxlrd->region_id));
> } while (IS_ERR(cxlr) && PTR_ERR(cxlr) == -EBUSY);
>
> @@ -3416,9 +3432,9 @@ static int cxl_region_probe(struct device *dev)
> return rc;
>
> switch (cxlr->mode) {
> - case CXL_DECODER_PMEM:
> + case CXL_PARTMODE_PMEM:
> return devm_cxl_add_pmem_region(cxlr);
> - case CXL_DECODER_RAM:
> + case CXL_PARTMODE_RAM:
> /*
> * The region can not be manged by CXL if any portion of
> * it is already online as 'System RAM'
next prev parent reply other threads:[~2025-01-23 16:51 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-22 8:59 [PATCH v2 0/5] cxl: DPA partition metadata is a mess Dan Williams
2025-01-22 8:59 ` [PATCH v2 1/5] cxl: Remove the CXL_DECODER_MIXED mistake Dan Williams
2025-01-22 14:11 ` Ira Weiny
2025-01-23 15:49 ` Jonathan Cameron
2025-01-23 15:58 ` Alejandro Lucero Palau
2025-01-23 16:03 ` Dave Jiang
2025-01-22 8:59 ` [PATCH v2 2/5] cxl: Introduce to_{ram,pmem}_{res,perf}() helpers Dan Williams
2025-01-22 14:18 ` Ira Weiny
2025-01-23 15:57 ` Jonathan Cameron
2025-01-23 20:01 ` Dan Williams
2025-01-23 16:13 ` Dave Jiang
2025-01-23 16:25 ` Alejandro Lucero Palau
2025-01-23 21:04 ` Dan Williams
2025-01-24 10:15 ` Alejandro Lucero Palau
2025-01-25 0:45 ` Dan Williams
2025-01-22 8:59 ` [PATCH v2 3/5] cxl: Introduce 'struct cxl_dpa_partition' and 'struct cxl_range_info' Dan Williams
2025-01-22 14:53 ` Ira Weiny
2025-01-22 22:24 ` Dan Williams
2025-01-23 3:10 ` Ira Weiny
2025-01-23 16:09 ` Jonathan Cameron
2025-01-23 20:24 ` Dan Williams
2025-01-23 16:57 ` Dave Jiang
2025-01-23 17:00 ` Alejandro Lucero Palau
2025-01-23 22:43 ` Dan Williams
2025-01-23 17:17 ` Alejandro Lucero Palau
2025-01-23 22:48 ` Dan Williams
2025-01-24 10:29 ` Alejandro Lucero Palau
2025-01-22 8:59 ` [PATCH v2 4/5] cxl: Make cxl_dpa_alloc() DPA partition number agnostic Dan Williams
2025-01-22 16:29 ` Ira Weiny
2025-01-22 22:35 ` Dan Williams
2025-01-23 3:14 ` Ira Weiny
2025-01-23 3:28 ` Dan Williams
2025-01-23 16:41 ` Jonathan Cameron
2025-01-23 21:34 ` Dan Williams
2025-01-23 17:21 ` Alejandro Lucero Palau
2025-01-23 20:52 ` Dave Jiang
2025-01-22 8:59 ` [PATCH v2 5/5] cxl: Kill enum cxl_decoder_mode Dan Williams
2025-01-22 17:42 ` Ira Weiny
2025-01-22 22:58 ` Dan Williams
2025-01-23 3:39 ` Ira Weiny
2025-01-23 4:11 ` Dan Williams
2025-01-23 21:30 ` Dave Jiang
2025-01-24 22:22 ` Ira Weiny
2025-01-23 16:51 ` Jonathan Cameron [this message]
2025-01-23 21:50 ` Dan Williams
2025-01-23 17:20 ` Alejandro Lucero Palau
2025-01-23 21:29 ` Dave Jiang
2025-01-23 17:23 ` [PATCH v2 0/5] cxl: DPA partition metadata is a mess Alejandro Lucero Palau
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