From: Tariq Toukan <tariqt@nvidia.com>
To: "David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Eric Dumazet <edumazet@google.com>,
"Andrew Lunn" <andrew+netdev@lunn.ch>
Cc: <netdev@vger.kernel.org>, Saeed Mahameed <saeedm@nvidia.com>,
Gal Pressman <gal@nvidia.com>, Jianbo Liu <jianbol@nvidia.com>,
Moshe Shemesh <moshe@nvidia.com>,
Leon Romanovsky <leonro@nvidia.com>,
Mark Bloch <mbloch@nvidia.com>,
Shahar Shitrit <shshitrit@nvidia.com>,
Tariq Toukan <tariqt@nvidia.com>
Subject: [PATCH net-next 10/15] ethtool: Add support for 200Gbps per lane link modes
Date: Mon, 3 Feb 2025 23:35:11 +0200 [thread overview]
Message-ID: <20250203213516.227902-11-tariqt@nvidia.com> (raw)
In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com>
From: Jianbo Liu <jianbol@nvidia.com>
Define 200G, 400G and 800G link modes using 200Gbps per lane.
Signed-off-by: Jianbo Liu <jianbol@nvidia.com>
Reviewed-by: Shahar Shitrit <shshitrit@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
---
drivers/net/phy/phy-core.c | 20 ++++++++++++++++-
include/uapi/linux/ethtool.h | 18 ++++++++++++++++
net/ethtool/common.c | 42 ++++++++++++++++++++++++++++++++++++
3 files changed, 79 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 6bf3ec985f3d..f181f05cb429 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -13,7 +13,7 @@
*/
const char *phy_speed_to_str(int speed)
{
- BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 103,
+ BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 121,
"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
"If a speed or mode has been added please update phy_speed_to_str "
"and the PHY settings array.\n");
@@ -169,6 +169,12 @@ static const struct phy_setting settings[] = {
PHY_SETTING( 800000, FULL, 800000baseDR8_2_Full ),
PHY_SETTING( 800000, FULL, 800000baseSR8_Full ),
PHY_SETTING( 800000, FULL, 800000baseVR8_Full ),
+ PHY_SETTING( 800000, FULL, 800000baseCR4_Full ),
+ PHY_SETTING( 800000, FULL, 800000baseKR4_Full ),
+ PHY_SETTING( 800000, FULL, 800000baseDR4_Full ),
+ PHY_SETTING( 800000, FULL, 800000baseDR4_2_Full ),
+ PHY_SETTING( 800000, FULL, 800000baseSR4_Full ),
+ PHY_SETTING( 800000, FULL, 800000baseVR4_Full ),
/* 400G */
PHY_SETTING( 400000, FULL, 400000baseCR8_Full ),
PHY_SETTING( 400000, FULL, 400000baseKR8_Full ),
@@ -180,6 +186,12 @@ static const struct phy_setting settings[] = {
PHY_SETTING( 400000, FULL, 400000baseLR4_ER4_FR4_Full ),
PHY_SETTING( 400000, FULL, 400000baseDR4_Full ),
PHY_SETTING( 400000, FULL, 400000baseSR4_Full ),
+ PHY_SETTING( 400000, FULL, 400000baseCR2_Full ),
+ PHY_SETTING( 400000, FULL, 400000baseKR2_Full ),
+ PHY_SETTING( 400000, FULL, 400000baseDR2_Full ),
+ PHY_SETTING( 400000, FULL, 400000baseDR2_2_Full ),
+ PHY_SETTING( 400000, FULL, 400000baseSR2_Full ),
+ PHY_SETTING( 400000, FULL, 400000baseVR2_Full ),
/* 200G */
PHY_SETTING( 200000, FULL, 200000baseCR4_Full ),
PHY_SETTING( 200000, FULL, 200000baseKR4_Full ),
@@ -191,6 +203,12 @@ static const struct phy_setting settings[] = {
PHY_SETTING( 200000, FULL, 200000baseLR2_ER2_FR2_Full ),
PHY_SETTING( 200000, FULL, 200000baseDR2_Full ),
PHY_SETTING( 200000, FULL, 200000baseSR2_Full ),
+ PHY_SETTING( 200000, FULL, 200000baseCR_Full ),
+ PHY_SETTING( 200000, FULL, 200000baseKR_Full ),
+ PHY_SETTING( 200000, FULL, 200000baseDR_Full ),
+ PHY_SETTING( 200000, FULL, 200000baseDR_2_Full ),
+ PHY_SETTING( 200000, FULL, 200000baseSR_Full ),
+ PHY_SETTING( 200000, FULL, 200000baseVR_Full ),
/* 100G */
PHY_SETTING( 100000, FULL, 100000baseCR4_Full ),
PHY_SETTING( 100000, FULL, 100000baseKR4_Full ),
diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index d1089b88efc7..e0bd726f84c1 100644
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -2057,6 +2057,24 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100,
ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101,
ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT = 102,
+ ETHTOOL_LINK_MODE_200000baseCR_Full_BIT = 103,
+ ETHTOOL_LINK_MODE_200000baseKR_Full_BIT = 104,
+ ETHTOOL_LINK_MODE_200000baseDR_Full_BIT = 105,
+ ETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT = 106,
+ ETHTOOL_LINK_MODE_200000baseSR_Full_BIT = 107,
+ ETHTOOL_LINK_MODE_200000baseVR_Full_BIT = 108,
+ ETHTOOL_LINK_MODE_400000baseCR2_Full_BIT = 109,
+ ETHTOOL_LINK_MODE_400000baseKR2_Full_BIT = 110,
+ ETHTOOL_LINK_MODE_400000baseDR2_Full_BIT = 111,
+ ETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT = 112,
+ ETHTOOL_LINK_MODE_400000baseSR2_Full_BIT = 113,
+ ETHTOOL_LINK_MODE_400000baseVR2_Full_BIT = 114,
+ ETHTOOL_LINK_MODE_800000baseCR4_Full_BIT = 115,
+ ETHTOOL_LINK_MODE_800000baseKR4_Full_BIT = 116,
+ ETHTOOL_LINK_MODE_800000baseDR4_Full_BIT = 117,
+ ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT = 118,
+ ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT = 119,
+ ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT = 120,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
diff --git a/net/ethtool/common.c b/net/ethtool/common.c
index 2bd77c94f9f1..5489d0c9d13f 100644
--- a/net/ethtool/common.c
+++ b/net/ethtool/common.c
@@ -213,6 +213,24 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
__DEFINE_LINK_MODE_NAME(10, T1S, Half),
__DEFINE_LINK_MODE_NAME(10, T1S_P2MP, Half),
__DEFINE_LINK_MODE_NAME(10, T1BRR, Full),
+ __DEFINE_LINK_MODE_NAME(200000, CR, Full),
+ __DEFINE_LINK_MODE_NAME(200000, KR, Full),
+ __DEFINE_LINK_MODE_NAME(200000, DR, Full),
+ __DEFINE_LINK_MODE_NAME(200000, DR_2, Full),
+ __DEFINE_LINK_MODE_NAME(200000, SR, Full),
+ __DEFINE_LINK_MODE_NAME(200000, VR, Full),
+ __DEFINE_LINK_MODE_NAME(400000, CR2, Full),
+ __DEFINE_LINK_MODE_NAME(400000, KR2, Full),
+ __DEFINE_LINK_MODE_NAME(400000, DR2, Full),
+ __DEFINE_LINK_MODE_NAME(400000, DR2_2, Full),
+ __DEFINE_LINK_MODE_NAME(400000, SR2, Full),
+ __DEFINE_LINK_MODE_NAME(400000, VR2, Full),
+ __DEFINE_LINK_MODE_NAME(800000, CR4, Full),
+ __DEFINE_LINK_MODE_NAME(800000, KR4, Full),
+ __DEFINE_LINK_MODE_NAME(800000, DR4, Full),
+ __DEFINE_LINK_MODE_NAME(800000, DR4_2, Full),
+ __DEFINE_LINK_MODE_NAME(800000, SR4, Full),
+ __DEFINE_LINK_MODE_NAME(800000, VR4, Full),
};
static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
@@ -221,8 +239,11 @@ static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
#define __LINK_MODE_LANES_CR4 4
#define __LINK_MODE_LANES_CR8 8
#define __LINK_MODE_LANES_DR 1
+#define __LINK_MODE_LANES_DR_2 1
#define __LINK_MODE_LANES_DR2 2
+#define __LINK_MODE_LANES_DR2_2 2
#define __LINK_MODE_LANES_DR4 4
+#define __LINK_MODE_LANES_DR4_2 4
#define __LINK_MODE_LANES_DR8 8
#define __LINK_MODE_LANES_KR 1
#define __LINK_MODE_LANES_KR2 2
@@ -251,6 +272,9 @@ static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
#define __LINK_MODE_LANES_T1L 1
#define __LINK_MODE_LANES_T1S 1
#define __LINK_MODE_LANES_T1S_P2MP 1
+#define __LINK_MODE_LANES_VR 1
+#define __LINK_MODE_LANES_VR2 2
+#define __LINK_MODE_LANES_VR4 4
#define __LINK_MODE_LANES_VR8 8
#define __LINK_MODE_LANES_DR8_2 8
#define __LINK_MODE_LANES_T1BRR 1
@@ -378,6 +402,24 @@ const struct link_mode_info link_mode_params[] = {
__DEFINE_LINK_MODE_PARAMS(10, T1S, Half),
__DEFINE_LINK_MODE_PARAMS(10, T1S_P2MP, Half),
__DEFINE_LINK_MODE_PARAMS(10, T1BRR, Full),
+ __DEFINE_LINK_MODE_PARAMS(200000, CR, Full),
+ __DEFINE_LINK_MODE_PARAMS(200000, KR, Full),
+ __DEFINE_LINK_MODE_PARAMS(200000, DR, Full),
+ __DEFINE_LINK_MODE_PARAMS(200000, DR_2, Full),
+ __DEFINE_LINK_MODE_PARAMS(200000, SR, Full),
+ __DEFINE_LINK_MODE_PARAMS(200000, VR, Full),
+ __DEFINE_LINK_MODE_PARAMS(400000, CR2, Full),
+ __DEFINE_LINK_MODE_PARAMS(400000, KR2, Full),
+ __DEFINE_LINK_MODE_PARAMS(400000, DR2, Full),
+ __DEFINE_LINK_MODE_PARAMS(400000, DR2_2, Full),
+ __DEFINE_LINK_MODE_PARAMS(400000, SR2, Full),
+ __DEFINE_LINK_MODE_PARAMS(400000, VR2, Full),
+ __DEFINE_LINK_MODE_PARAMS(800000, CR4, Full),
+ __DEFINE_LINK_MODE_PARAMS(800000, KR4, Full),
+ __DEFINE_LINK_MODE_PARAMS(800000, DR4, Full),
+ __DEFINE_LINK_MODE_PARAMS(800000, DR4_2, Full),
+ __DEFINE_LINK_MODE_PARAMS(800000, SR4, Full),
+ __DEFINE_LINK_MODE_PARAMS(800000, VR4, Full),
};
static_assert(ARRAY_SIZE(link_mode_params) == __ETHTOOL_LINK_MODE_MASK_NBITS);
--
2.45.0
next prev parent reply other threads:[~2025-02-03 21:37 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-03 21:35 [PATCH net-next 00/15] Support one PTP device per hardware clock Tariq Toukan
2025-02-03 21:35 ` [PATCH net-next 01/15] net/mlx5: Add helper functions for PTP callbacks Tariq Toukan
2025-02-04 8:43 ` Mateusz Polchlopek
2025-02-05 6:04 ` Tariq Toukan
2025-02-03 21:35 ` [PATCH net-next 02/15] net/mlx5: Change parameters for PTP internal functions Tariq Toukan
2025-02-04 8:51 ` Mateusz Polchlopek
2025-02-05 6:08 ` Tariq Toukan
2025-02-03 21:35 ` [PATCH net-next 03/15] net/mlx5: Add init and destruction functions for a single HW clock Tariq Toukan
2025-02-03 21:35 ` [PATCH net-next 04/15] net/mlx5: Add API to get mlx5_core_dev from mlx5_clock Tariq Toukan
2025-02-03 21:35 ` [PATCH net-next 05/15] net/mlx5: Change clock in mlx5_core_dev to mlx5_clock pointer Tariq Toukan
2025-02-03 21:35 ` [PATCH net-next 06/15] net/mlx5: Add devcom component for the clock shared by functions Tariq Toukan
2025-02-03 21:35 ` [PATCH net-next 07/15] net/mlx5: Move PPS notifier and out_work to clock_state Tariq Toukan
2025-02-03 21:35 ` [PATCH net-next 08/15] net/mlx5: Support one PTP device per hardware clock Tariq Toukan
2025-02-03 21:35 ` [PATCH net-next 09/15] net/mlx5: Generate PPS IN event on new function for shared clock Tariq Toukan
2025-02-03 21:35 ` Tariq Toukan [this message]
2025-02-03 21:35 ` [PATCH net-next 11/15] net/mlx5: Add support for 200Gbps per lane link modes Tariq Toukan
2025-02-03 21:35 ` [PATCH net-next 12/15] net/mlx5e: Support FEC settings for 200G " Tariq Toukan
2025-02-03 21:35 ` [PATCH net-next 13/15] net/mlx5: Remove stray semicolon in LAG port selection table creation Tariq Toukan
2025-02-04 8:21 ` Kalesh Anakkur Purayil
2025-02-03 21:35 ` [PATCH net-next 14/15] net/mlx5e: Remove unused mlx5e_tc_flow_action struct Tariq Toukan
2025-02-04 8:22 ` Kalesh Anakkur Purayil
2025-02-03 21:35 ` [PATCH net-next 15/15] net/mlx5e: Avoid WARN_ON when configuring MQPRIO with HTB offload enabled Tariq Toukan
2025-02-04 8:21 ` Kalesh Anakkur Purayil
2025-02-05 6:14 ` [PATCH net-next 00/15] Support one PTP device per hardware clock Tariq Toukan
2025-02-06 9:09 ` Paolo Abeni
2025-02-06 9:40 ` patchwork-bot+netdevbpf
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