From: Rob Herring <robh@kernel.org>
To: Anup Patel <apatel@ventanamicro.com>
Cc: "Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Jassi Brar" <jassisinghbrar@gmail.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"Mika Westerberg" <mika.westerberg@linux.intel.com>,
"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Bartosz Golaszewski" <brgl@bgdev.pl>,
"Uwe Kleine-König" <ukleinek@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Len Brown" <lenb@kernel.org>,
"Sunil V L" <sunilvl@ventanamicro.com>,
"Rahul Pathak" <rpathak@ventanamicro.com>,
"Leyfoon Tan" <leyfoon.tan@starfivetech.com>,
"Atish Patra" <atishp@atishpatra.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Anup Patel" <anup@brainfault.org>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH v2 02/17] dt-bindings: mailbox: Add bindings for RPMI shared memory transport
Date: Mon, 3 Feb 2025 16:30:20 -0600 [thread overview]
Message-ID: <20250203223020.GA277987-robh@kernel.org> (raw)
In-Reply-To: <20250203084906.681418-3-apatel@ventanamicro.com>
On Mon, Feb 03, 2025 at 02:18:51PM +0530, Anup Patel wrote:
> Add device tree bindings for the common RISC-V Platform Management
> Interface (RPMI) shared memory transport as a mailbox controller.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> .../mailbox/riscv,rpmi-shmem-mbox.yaml | 150 ++++++++++++++++++
> 1 file changed, 150 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml
>
> diff --git a/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml b/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml
> new file mode 100644
> index 000000000000..c339df5d9e24
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml
> @@ -0,0 +1,150 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mailbox/riscv,rpmi-shmem-mbox.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V Platform Management Interface (RPMI) shared memory mailbox
> +
> +maintainers:
> + - Anup Patel <anup@brainfault.org>
> +
> +description: |
> + The RISC-V Platform Management Interface (RPMI) [1] defines a common shared
> + memory based RPMI transport. This RPMI shared memory transport integrates as
> + mailbox controller in the SBI implementation or supervisor software whereas
> + each RPMI service group is mailbox client in the SBI implementation and
> + supervisor software.
> +
> + ===========================================
> + References
> + ===========================================
> +
> + [1] RISC-V Platform Management Interface (RPMI)
> + https://github.com/riscv-non-isa/riscv-rpmi/releases
> +
> +properties:
> + compatible:
> + const: riscv,rpmi-shmem-mbox
> +
> + reg:
> + oneOf:
> + - items:
> + - description: A2P request queue base address
> + - description: P2A acknowledgment queue base address
> + - description: P2A request queue base address
> + - description: A2P acknowledgment queue base address
> + - description: A2P doorbell address
> + - items:
> + - description: A2P request queue base address
> + - description: P2A acknowledgment queue base address
> + - description: P2A request queue base address
> + - description: A2P acknowledgment queue base address
> + - items:
> + - description: A2P request queue base address
> + - description: P2A acknowledgment queue base address
> + - description: A2P doorbell address
> + - items:
> + - description: A2P request queue base address
> + - description: P2A acknowledgment queue base address
> +
> + reg-names:
> + oneOf:
> + - items:
> + - const: a2p-req
> + - const: p2a-ack
> + - const: p2a-req
> + - const: a2p-ack
> + - const: doorbell
> + - items:
> + - const: a2p-req
> + - const: p2a-ack
> + - const: p2a-req
> + - const: a2p-ack
These first 2 items lists can be combined with the addition of
'minItems: 4'
> + - items:
> + - const: a2p-req
> + - const: p2a-ack
> + - const: doorbell
> + - items:
> + - const: a2p-req
> + - const: p2a-ack
> +
> + interrupts:
> + maxItems: 1
> + description:
> + The RPMI shared memory transport supports wired interrupt specified by
> + this property as the P2A doorbell.
> +
> + msi-parent:
> + description:
> + The RPMI shared memory transport supports MSI as P2A doorbell and this
> + property specifies the target MSI controller.
> +
> + riscv,slot-size:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 64
> + description:
> + Power-of-2 RPMI slot size of the RPMI shared memory transport.
> +
> + riscv,doorbell-mask:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0xffffffff
> + description:
> + Update only the register bits of doorbell defined by the mask (32 bit).
> +
> + riscv,doorbell-value:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0x1
> + description:
> + Value written to the doorbell register bits (32-bit access) specified
> + by the riscv,db-mask property.
You mean riscv,doorbell-mask?
I'm confused why you would need both? If the value to write is fixed
here, then why do you need a mask? You could just mask the value here.
I assume there's some dependency between these 2 properties. That needs
to be captured with 'dependencies'.
> +
> + "#mbox-cells":
> + const: 1
> + description:
> + The first cell specifies RPMI service group ID.
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - riscv,slot-size
> + - "#mbox-cells"
> +
> +anyOf:
> + - required:
> + - interrupts
> + - required:
> + - msi-parent
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + // Example 1 (RPMI shared memory with only 2 queues):
> + mailbox@10080000 {
> + compatible = "riscv,rpmi-shmem-mbox";
> + reg = <0x10080000 0x10000>,
> + <0x10090000 0x10000>,
> + <0x100a0000 0x4>;
> + reg-names = "a2p-req", "p2a-ack", "doorbell";
> + msi-parent = <&imsic_mlevel>;
> + riscv,slot-size = <64>;
> + #mbox-cells = <1>;
> + };
> + - |
> + // Example 2 (RPMI shared memory with only 4 queues):
> + mailbox@10001000 {
> + compatible = "riscv,rpmi-shmem-mbox";
> + reg = <0x10001000 0x800>,
> + <0x10001800 0x800>,
> + <0x10002000 0x800>,
> + <0x10002800 0x800>,
> + <0x10003000 0x4>;
> + reg-names = "a2p-req", "p2a-ack", "p2a-req", "a2p-ack", "doorbell";
> + msi-parent = <&imsic_mlevel>;
> + riscv,slot-size = <64>;
> + riscv,doorbell-mask = <0x00008000>;
> + riscv,doorbell-value = <0x00008000>;
> + #mbox-cells = <1>;
> + };
> --
> 2.43.0
>
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Anup Patel <apatel@ventanamicro.com>
Cc: "Rafael J . Wysocki" <rafael@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Uwe Kleine-König" <ukleinek@kernel.org>,
linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org,
"Anup Patel" <anup@brainfault.org>,
"Bartosz Golaszewski" <brgl@bgdev.pl>,
"Jassi Brar" <jassisinghbrar@gmail.com>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Rahul Pathak" <rpathak@ventanamicro.com>,
devicetree@vger.kernel.org, "Conor Dooley" <conor+dt@kernel.org>,
"Leyfoon Tan" <leyfoon.tan@starfivetech.com>,
"Atish Patra" <atishp@atishpatra.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
"Mika Westerberg" <mika.westerberg@linux.intel.com>,
"Stephen Boyd" <sboyd@kernel.org>,
linux-kernel@vger.kernel.org,
"Samuel Holland" <samuel.holland@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Len Brown" <lenb@kernel.org>
Subject: Re: [RFC PATCH v2 02/17] dt-bindings: mailbox: Add bindings for RPMI shared memory transport
Date: Mon, 3 Feb 2025 16:30:20 -0600 [thread overview]
Message-ID: <20250203223020.GA277987-robh@kernel.org> (raw)
In-Reply-To: <20250203084906.681418-3-apatel@ventanamicro.com>
On Mon, Feb 03, 2025 at 02:18:51PM +0530, Anup Patel wrote:
> Add device tree bindings for the common RISC-V Platform Management
> Interface (RPMI) shared memory transport as a mailbox controller.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> .../mailbox/riscv,rpmi-shmem-mbox.yaml | 150 ++++++++++++++++++
> 1 file changed, 150 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml
>
> diff --git a/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml b/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml
> new file mode 100644
> index 000000000000..c339df5d9e24
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml
> @@ -0,0 +1,150 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mailbox/riscv,rpmi-shmem-mbox.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V Platform Management Interface (RPMI) shared memory mailbox
> +
> +maintainers:
> + - Anup Patel <anup@brainfault.org>
> +
> +description: |
> + The RISC-V Platform Management Interface (RPMI) [1] defines a common shared
> + memory based RPMI transport. This RPMI shared memory transport integrates as
> + mailbox controller in the SBI implementation or supervisor software whereas
> + each RPMI service group is mailbox client in the SBI implementation and
> + supervisor software.
> +
> + ===========================================
> + References
> + ===========================================
> +
> + [1] RISC-V Platform Management Interface (RPMI)
> + https://github.com/riscv-non-isa/riscv-rpmi/releases
> +
> +properties:
> + compatible:
> + const: riscv,rpmi-shmem-mbox
> +
> + reg:
> + oneOf:
> + - items:
> + - description: A2P request queue base address
> + - description: P2A acknowledgment queue base address
> + - description: P2A request queue base address
> + - description: A2P acknowledgment queue base address
> + - description: A2P doorbell address
> + - items:
> + - description: A2P request queue base address
> + - description: P2A acknowledgment queue base address
> + - description: P2A request queue base address
> + - description: A2P acknowledgment queue base address
> + - items:
> + - description: A2P request queue base address
> + - description: P2A acknowledgment queue base address
> + - description: A2P doorbell address
> + - items:
> + - description: A2P request queue base address
> + - description: P2A acknowledgment queue base address
> +
> + reg-names:
> + oneOf:
> + - items:
> + - const: a2p-req
> + - const: p2a-ack
> + - const: p2a-req
> + - const: a2p-ack
> + - const: doorbell
> + - items:
> + - const: a2p-req
> + - const: p2a-ack
> + - const: p2a-req
> + - const: a2p-ack
These first 2 items lists can be combined with the addition of
'minItems: 4'
> + - items:
> + - const: a2p-req
> + - const: p2a-ack
> + - const: doorbell
> + - items:
> + - const: a2p-req
> + - const: p2a-ack
> +
> + interrupts:
> + maxItems: 1
> + description:
> + The RPMI shared memory transport supports wired interrupt specified by
> + this property as the P2A doorbell.
> +
> + msi-parent:
> + description:
> + The RPMI shared memory transport supports MSI as P2A doorbell and this
> + property specifies the target MSI controller.
> +
> + riscv,slot-size:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 64
> + description:
> + Power-of-2 RPMI slot size of the RPMI shared memory transport.
> +
> + riscv,doorbell-mask:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0xffffffff
> + description:
> + Update only the register bits of doorbell defined by the mask (32 bit).
> +
> + riscv,doorbell-value:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0x1
> + description:
> + Value written to the doorbell register bits (32-bit access) specified
> + by the riscv,db-mask property.
You mean riscv,doorbell-mask?
I'm confused why you would need both? If the value to write is fixed
here, then why do you need a mask? You could just mask the value here.
I assume there's some dependency between these 2 properties. That needs
to be captured with 'dependencies'.
> +
> + "#mbox-cells":
> + const: 1
> + description:
> + The first cell specifies RPMI service group ID.
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - riscv,slot-size
> + - "#mbox-cells"
> +
> +anyOf:
> + - required:
> + - interrupts
> + - required:
> + - msi-parent
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + // Example 1 (RPMI shared memory with only 2 queues):
> + mailbox@10080000 {
> + compatible = "riscv,rpmi-shmem-mbox";
> + reg = <0x10080000 0x10000>,
> + <0x10090000 0x10000>,
> + <0x100a0000 0x4>;
> + reg-names = "a2p-req", "p2a-ack", "doorbell";
> + msi-parent = <&imsic_mlevel>;
> + riscv,slot-size = <64>;
> + #mbox-cells = <1>;
> + };
> + - |
> + // Example 2 (RPMI shared memory with only 4 queues):
> + mailbox@10001000 {
> + compatible = "riscv,rpmi-shmem-mbox";
> + reg = <0x10001000 0x800>,
> + <0x10001800 0x800>,
> + <0x10002000 0x800>,
> + <0x10002800 0x800>,
> + <0x10003000 0x4>;
> + reg-names = "a2p-req", "p2a-ack", "p2a-req", "a2p-ack", "doorbell";
> + msi-parent = <&imsic_mlevel>;
> + riscv,slot-size = <64>;
> + riscv,doorbell-mask = <0x00008000>;
> + riscv,doorbell-value = <0x00008000>;
> + #mbox-cells = <1>;
> + };
> --
> 2.43.0
>
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next prev parent reply other threads:[~2025-02-03 22:30 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-03 8:48 [RFC PATCH v2 00/17] Linux SBI MPXY and RPMI drivers Anup Patel
2025-02-03 8:48 ` Anup Patel
2025-02-03 8:48 ` [RFC PATCH v2 01/17] riscv: Add new error codes defined by SBI v3.0 Anup Patel
2025-02-03 8:48 ` Anup Patel
2025-02-03 8:48 ` [RFC PATCH v2 02/17] dt-bindings: mailbox: Add bindings for RPMI shared memory transport Anup Patel
2025-02-03 8:48 ` Anup Patel
2025-02-03 22:30 ` Rob Herring [this message]
2025-02-03 22:30 ` Rob Herring
2025-05-02 9:15 ` Anup Patel
2025-05-02 9:15 ` Anup Patel
2025-02-03 8:48 ` [RFC PATCH v2 03/17] dt-bindings: mailbox: Add bindings for RISC-V SBI MPXY extension Anup Patel
2025-02-03 8:48 ` Anup Patel
2025-02-03 22:44 ` Rob Herring
2025-02-03 22:44 ` Rob Herring
2025-02-06 12:32 ` Anup Patel
2025-02-06 12:32 ` Anup Patel
2025-02-03 8:48 ` [RFC PATCH v2 04/17] RISC-V: Add defines for the SBI message proxy extension Anup Patel
2025-02-03 8:48 ` Anup Patel
2025-02-03 8:48 ` [RFC PATCH v2 05/17] mailbox: Add common header for RPMI messages sent via mailbox Anup Patel
2025-02-03 8:48 ` Anup Patel
2025-02-03 8:48 ` [RFC PATCH v2 06/17] mailbox: Allow controller specific mapping using fwnode Anup Patel
2025-02-03 8:48 ` Anup Patel
2025-02-03 8:48 ` [RFC PATCH v2 07/17] mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver Anup Patel
2025-02-03 8:48 ` Anup Patel
2025-02-03 8:48 ` [RFC PATCH v2 08/17] dt-bindings: clock: Add bindings for RISC-V RPMI clock service group Anup Patel
2025-02-03 8:48 ` Anup Patel
2025-02-03 22:51 ` Rob Herring
2025-02-03 22:51 ` Rob Herring
2025-05-04 10:30 ` Anup Patel
2025-05-04 10:30 ` Anup Patel
2025-02-03 8:48 ` [RFC PATCH v2 09/17] clk: Add clock driver for the " Anup Patel
2025-02-03 8:48 ` Anup Patel
2025-02-03 8:48 ` [RFC PATCH v2 10/17] dt-bindings: interrupt-controller: Add bindings for RISC-V RPMI system MSI Anup Patel
2025-02-03 8:48 ` Anup Patel
2025-02-03 22:58 ` Rob Herring
2025-02-03 22:58 ` Rob Herring
2025-05-04 10:44 ` Anup Patel
2025-05-04 10:44 ` Anup Patel
2025-02-03 8:49 ` [RFC PATCH v2 11/17] irqchip: Add driver for the RISC-V RPMI system MSI service group Anup Patel
2025-02-03 8:49 ` Anup Patel
2025-02-03 13:50 ` Thomas Gleixner
2025-02-03 13:50 ` Thomas Gleixner
2025-02-06 12:17 ` Anup Patel
2025-02-06 12:17 ` Anup Patel
2025-02-03 8:49 ` [RFC PATCH v2 12/17] ACPI: property: Add support for nargs_prop in acpi_fwnode_get_reference_args() Anup Patel
2025-02-03 8:49 ` Anup Patel
2025-02-03 9:43 ` Andy Shevchenko
2025-02-03 9:43 ` Andy Shevchenko
2025-02-03 10:58 ` Mika Westerberg
2025-02-03 10:58 ` Mika Westerberg
2025-02-03 12:24 ` Sunil V L
2025-02-03 12:24 ` Sunil V L
2025-02-03 12:36 ` Mika Westerberg
2025-02-03 12:36 ` Mika Westerberg
2025-02-03 13:51 ` Sunil V L
2025-02-03 13:51 ` Sunil V L
2025-02-03 14:39 ` Andy Shevchenko
2025-02-03 14:39 ` Andy Shevchenko
2025-02-03 14:41 ` Andy Shevchenko
2025-02-03 14:41 ` Andy Shevchenko
2025-02-04 16:58 ` Sunil V L
2025-02-04 16:58 ` Sunil V L
2025-02-04 17:36 ` Andy Shevchenko
2025-02-04 17:36 ` Andy Shevchenko
2025-02-03 8:49 ` [RFC PATCH v2 13/17] ACPI: scan: Update honor list for RPMI System MSI Anup Patel
2025-02-03 8:49 ` Anup Patel
2025-02-03 8:49 ` [RFC PATCH v2 14/17] ACPI: RISC-V: Add RPMI System MSI to GSI mapping Anup Patel
2025-02-03 8:49 ` Anup Patel
2025-02-03 8:49 ` [RFC PATCH v2 15/17] mailbox/riscv-sbi-mpxy: Add ACPI support Anup Patel
2025-02-03 8:49 ` Anup Patel
2025-02-03 9:45 ` Andy Shevchenko
2025-02-03 9:45 ` Andy Shevchenko
2025-02-03 8:49 ` [RFC PATCH v2 16/17] irqchip/riscv-rpmi-sysmsi: " Anup Patel
2025-02-03 8:49 ` Anup Patel
2025-02-03 9:38 ` Andy Shevchenko
2025-02-03 9:38 ` Andy Shevchenko
2025-02-04 4:18 ` Sunil V L
2025-02-04 4:18 ` Sunil V L
2025-02-03 13:52 ` Thomas Gleixner
2025-02-03 13:52 ` Thomas Gleixner
2025-02-03 8:49 ` [RFC PATCH v2 17/17] RISC-V: Enable GPIO keyboard and event device in RV64 defconfig Anup Patel
2025-02-03 8:49 ` Anup Patel
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