All of lore.kernel.org
 help / color / mirror / Atom feed
From: Palmer Dabbelt <palmer@rivosinc.com>
To: linux-riscv@lists.infradead.org
Cc: alex@ghiti.fr, Charlie Jenkins <charlie@rivosinc.com>,
	Mr.Bossman075@gmail.com, Jesse Taube <jesse@rivosinc.com>,
	Palmer Dabbelt <palmer@rivosinc.com>
Subject: [PATCH v2 1/2] RISC-V: hwprobe: Use BIT macro to avoid warnings
Date: Wed,  5 Feb 2025 12:40:26 -0800	[thread overview]
Message-ID: <20250205204129.10639-2-palmer@rivosinc.com> (raw)
In-Reply-To: <20250205204129.10639-1-palmer@rivosinc.com>

From: Jesse Taube <jesse@rivosinc.com>

In uapi/asm/hwprobe.h file, (1 << N) is used to define the bit field
which causes checkpatch to warn. Use BIT(N) and BIT_ULL(N) to avoid
these warnings.

Signed-off-by: Jesse Taube <jesse@rivosinc.com>
[Palmer: rebase and clean up a bit]
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/include/uapi/asm/hwprobe.h | 117 +++++++++++++-------------
 1 file changed, 59 insertions(+), 58 deletions(-)

diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index c3c1cc951cb9..600ca96ae55e 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -7,6 +7,7 @@
 #define _UAPI_ASM_HWPROBE_H
 
 #include <linux/types.h>
+#include <linux/const.h>
 
 /*
  * Interface for probing hardware capabilities from userspace, see
@@ -21,65 +22,65 @@ struct riscv_hwprobe {
 #define RISCV_HWPROBE_KEY_MARCHID	1
 #define RISCV_HWPROBE_KEY_MIMPID	2
 #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR	3
-#define		RISCV_HWPROBE_BASE_BEHAVIOR_IMA	(1 << 0)
+#define		RISCV_HWPROBE_BASE_BEHAVIOR_IMA	_BITULL(0)
 #define RISCV_HWPROBE_KEY_IMA_EXT_0	4
-#define		RISCV_HWPROBE_IMA_FD		(1 << 0)
-#define		RISCV_HWPROBE_IMA_C		(1 << 1)
-#define		RISCV_HWPROBE_IMA_V		(1 << 2)
-#define		RISCV_HWPROBE_EXT_ZBA		(1 << 3)
-#define		RISCV_HWPROBE_EXT_ZBB		(1 << 4)
-#define		RISCV_HWPROBE_EXT_ZBS		(1 << 5)
-#define		RISCV_HWPROBE_EXT_ZICBOZ	(1 << 6)
-#define		RISCV_HWPROBE_EXT_ZBC		(1 << 7)
-#define		RISCV_HWPROBE_EXT_ZBKB		(1 << 8)
-#define		RISCV_HWPROBE_EXT_ZBKC		(1 << 9)
-#define		RISCV_HWPROBE_EXT_ZBKX		(1 << 10)
-#define		RISCV_HWPROBE_EXT_ZKND		(1 << 11)
-#define		RISCV_HWPROBE_EXT_ZKNE		(1 << 12)
-#define		RISCV_HWPROBE_EXT_ZKNH		(1 << 13)
-#define		RISCV_HWPROBE_EXT_ZKSED		(1 << 14)
-#define		RISCV_HWPROBE_EXT_ZKSH		(1 << 15)
-#define		RISCV_HWPROBE_EXT_ZKT		(1 << 16)
-#define		RISCV_HWPROBE_EXT_ZVBB		(1 << 17)
-#define		RISCV_HWPROBE_EXT_ZVBC		(1 << 18)
-#define		RISCV_HWPROBE_EXT_ZVKB		(1 << 19)
-#define		RISCV_HWPROBE_EXT_ZVKG		(1 << 20)
-#define		RISCV_HWPROBE_EXT_ZVKNED	(1 << 21)
-#define		RISCV_HWPROBE_EXT_ZVKNHA	(1 << 22)
-#define		RISCV_HWPROBE_EXT_ZVKNHB	(1 << 23)
-#define		RISCV_HWPROBE_EXT_ZVKSED	(1 << 24)
-#define		RISCV_HWPROBE_EXT_ZVKSH		(1 << 25)
-#define		RISCV_HWPROBE_EXT_ZVKT		(1 << 26)
-#define		RISCV_HWPROBE_EXT_ZFH		(1 << 27)
-#define		RISCV_HWPROBE_EXT_ZFHMIN	(1 << 28)
-#define		RISCV_HWPROBE_EXT_ZIHINTNTL	(1 << 29)
-#define		RISCV_HWPROBE_EXT_ZVFH		(1 << 30)
-#define		RISCV_HWPROBE_EXT_ZVFHMIN	(1ULL << 31)
-#define		RISCV_HWPROBE_EXT_ZFA		(1ULL << 32)
-#define		RISCV_HWPROBE_EXT_ZTSO		(1ULL << 33)
-#define		RISCV_HWPROBE_EXT_ZACAS		(1ULL << 34)
-#define		RISCV_HWPROBE_EXT_ZICOND	(1ULL << 35)
-#define		RISCV_HWPROBE_EXT_ZIHINTPAUSE	(1ULL << 36)
-#define		RISCV_HWPROBE_EXT_ZVE32X	(1ULL << 37)
-#define		RISCV_HWPROBE_EXT_ZVE32F	(1ULL << 38)
-#define		RISCV_HWPROBE_EXT_ZVE64X	(1ULL << 39)
-#define		RISCV_HWPROBE_EXT_ZVE64F	(1ULL << 40)
-#define		RISCV_HWPROBE_EXT_ZVE64D	(1ULL << 41)
-#define		RISCV_HWPROBE_EXT_ZIMOP		(1ULL << 42)
-#define		RISCV_HWPROBE_EXT_ZCA		(1ULL << 43)
-#define		RISCV_HWPROBE_EXT_ZCB		(1ULL << 44)
-#define		RISCV_HWPROBE_EXT_ZCD		(1ULL << 45)
-#define		RISCV_HWPROBE_EXT_ZCF		(1ULL << 46)
-#define		RISCV_HWPROBE_EXT_ZCMOP		(1ULL << 47)
-#define		RISCV_HWPROBE_EXT_ZAWRS		(1ULL << 48)
-#define		RISCV_HWPROBE_EXT_SUPM		(1ULL << 49)
+#define		RISCV_HWPROBE_IMA_FD		_BITULL(0)
+#define		RISCV_HWPROBE_IMA_C		_BITULL(1)
+#define		RISCV_HWPROBE_IMA_V		_BITULL(2)
+#define		RISCV_HWPROBE_EXT_ZBA		_BITULL(3)
+#define		RISCV_HWPROBE_EXT_ZBB		_BITULL(4)
+#define		RISCV_HWPROBE_EXT_ZBS		_BITULL(5)
+#define		RISCV_HWPROBE_EXT_ZICBOZ	_BITULL(6)
+#define		RISCV_HWPROBE_EXT_ZBC		_BITULL(7)
+#define		RISCV_HWPROBE_EXT_ZBKB		_BITULL(8)
+#define		RISCV_HWPROBE_EXT_ZBKC		_BITULL(9)
+#define		RISCV_HWPROBE_EXT_ZBKX		_BITULL(10)
+#define		RISCV_HWPROBE_EXT_ZKND		_BITULL(11)
+#define		RISCV_HWPROBE_EXT_ZKNE		_BITULL(12)
+#define		RISCV_HWPROBE_EXT_ZKNH		_BITULL(13)
+#define		RISCV_HWPROBE_EXT_ZKSED		_BITULL(14)
+#define		RISCV_HWPROBE_EXT_ZKSH		_BITULL(15)
+#define		RISCV_HWPROBE_EXT_ZKT		_BITULL(16)
+#define		RISCV_HWPROBE_EXT_ZVBB		_BITULL(17)
+#define		RISCV_HWPROBE_EXT_ZVBC		_BITULL(18)
+#define		RISCV_HWPROBE_EXT_ZVKB		_BITULL(19)
+#define		RISCV_HWPROBE_EXT_ZVKG		_BITULL(20)
+#define		RISCV_HWPROBE_EXT_ZVKNED	_BITULL(21)
+#define		RISCV_HWPROBE_EXT_ZVKNHA	_BITULL(22)
+#define		RISCV_HWPROBE_EXT_ZVKNHB	_BITULL(23)
+#define		RISCV_HWPROBE_EXT_ZVKSED	_BITULL(24)
+#define		RISCV_HWPROBE_EXT_ZVKSH		_BITULL(25)
+#define		RISCV_HWPROBE_EXT_ZVKT		_BITULL(26)
+#define		RISCV_HWPROBE_EXT_ZFH		_BITULL(27)
+#define		RISCV_HWPROBE_EXT_ZFHMIN	_BITULL(28)
+#define		RISCV_HWPROBE_EXT_ZIHINTNTL	_BITULL(29)
+#define		RISCV_HWPROBE_EXT_ZVFH		_BITULL(30)
+#define		RISCV_HWPROBE_EXT_ZVFHMIN	_BITULL(31)
+#define		RISCV_HWPROBE_EXT_ZFA		_BITULL(32)
+#define		RISCV_HWPROBE_EXT_ZTSO		_BITULL(33)
+#define		RISCV_HWPROBE_EXT_ZACAS		_BITULL(34)
+#define		RISCV_HWPROBE_EXT_ZICOND	_BITULL(35)
+#define		RISCV_HWPROBE_EXT_ZIHINTPAUSE	_BITULL(36)
+#define		RISCV_HWPROBE_EXT_ZVE32X	_BITULL(37)
+#define		RISCV_HWPROBE_EXT_ZVE32F	_BITULL(38)
+#define		RISCV_HWPROBE_EXT_ZVE64X	_BITULL(39)
+#define		RISCV_HWPROBE_EXT_ZVE64F	_BITULL(40)
+#define		RISCV_HWPROBE_EXT_ZVE64D	_BITULL(41)
+#define		RISCV_HWPROBE_EXT_ZIMOP		_BITULL(42)
+#define		RISCV_HWPROBE_EXT_ZCA		_BITULL(43)
+#define		RISCV_HWPROBE_EXT_ZCB		_BITULL(44)
+#define		RISCV_HWPROBE_EXT_ZCD		_BITULL(45)
+#define		RISCV_HWPROBE_EXT_ZCF		_BITULL(46)
+#define		RISCV_HWPROBE_EXT_ZCMOP		_BITULL(47)
+#define		RISCV_HWPROBE_EXT_ZAWRS		_BITULL(48)
+#define		RISCV_HWPROBE_EXT_SUPM		_BITULL(49)
 #define RISCV_HWPROBE_KEY_CPUPERF_0	5
-#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
-#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
-#define		RISCV_HWPROBE_MISALIGNED_SLOW		(2 << 0)
-#define		RISCV_HWPROBE_MISALIGNED_FAST		(3 << 0)
-#define		RISCV_HWPROBE_MISALIGNED_UNSUPPORTED	(4 << 0)
-#define		RISCV_HWPROBE_MISALIGNED_MASK		(7 << 0)
+#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	0
+#define		RISCV_HWPROBE_MISALIGNED_EMULATED	1
+#define		RISCV_HWPROBE_MISALIGNED_SLOW		2
+#define		RISCV_HWPROBE_MISALIGNED_FAST		3
+#define		RISCV_HWPROBE_MISALIGNED_UNSUPPORTED	4
+#define		RISCV_HWPROBE_MISALIGNED_MASK		7
 #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE	6
 #define RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS	7
 #define RISCV_HWPROBE_KEY_TIME_CSR_FREQ	8
@@ -98,6 +99,6 @@ struct riscv_hwprobe {
 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
 
 /* Flags */
-#define RISCV_HWPROBE_WHICH_CPUS	(1 << 0)
+#define RISCV_HWPROBE_WHICH_CPUS	BIT(0)
 
 #endif
-- 
2.45.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2025-02-05 23:53 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-05 20:40 [PATCH v2 0/2] RISC-V: Use BIT_ULL(x) instead of 1ULL << x Palmer Dabbelt
2025-02-05 20:40 ` Palmer Dabbelt [this message]
2025-02-06  8:58   ` [PATCH v2 1/2] RISC-V: hwprobe: Use BIT macro to avoid warnings Andreas Schwab
2025-02-05 20:40 ` [PATCH v2 2/2] RISC-V: Use BIT_ULL(x) instead of 1ULL << x Palmer Dabbelt
2025-02-06  6:15   ` Tomasz Jeznach

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20250205204129.10639-2-palmer@rivosinc.com \
    --to=palmer@rivosinc.com \
    --cc=Mr.Bossman075@gmail.com \
    --cc=alex@ghiti.fr \
    --cc=charlie@rivosinc.com \
    --cc=jesse@rivosinc.com \
    --cc=linux-riscv@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.