From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Anton Johansson" <anjo@rev.ng>,
"Alistair Francis" <alistair@alistair23.me>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Thomas Huth" <thuth@redhat.com>,
"Jason Wang" <jasowang@redhat.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Alistair Francis" <alistair.francis@wdc.com>
Subject: [PATCH v4 07/16] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx
Date: Thu, 6 Feb 2025 12:33:12 +0100 [thread overview]
Message-ID: <20250206113321.94906-8-philmd@linaro.org> (raw)
In-Reply-To: <20250206113321.94906-1-philmd@linaro.org>
Extract the implicit MO_TE definition in order to replace
it by runtime variable in the next commit.
Mechanical change using:
$ for n in UW UL UQ UO SW SL SQ; do \
sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
$(git grep -l MO_TE$n target/microblaze); \
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/microblaze/translate.c | 36 +++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 24005f05b21..86efabb83b5 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -780,13 +780,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg)
static bool trans_lhu(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
}
static bool trans_lhur(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
}
static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
@@ -798,26 +798,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_lhui(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
}
static bool trans_lw(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
}
static bool trans_lwr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
}
static bool trans_lwea(DisasContext *dc, arg_typea *arg)
@@ -829,14 +829,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_lwi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
}
static bool trans_lwx(DisasContext *dc, arg_typea *arg)
@@ -846,7 +846,7 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
/* lwx does not throw unaligned access errors, so force alignment */
tcg_gen_andi_tl(addr, addr, ~3);
- tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL);
+ tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL);
tcg_gen_mov_tl(cpu_res_addr, addr);
if (arg->rd) {
@@ -930,13 +930,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg)
static bool trans_sh(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
}
static bool trans_shr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
}
static bool trans_shea(DisasContext *dc, arg_typea *arg)
@@ -948,26 +948,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_shi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
}
static bool trans_sw(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
}
static bool trans_swr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
}
static bool trans_swea(DisasContext *dc, arg_typea *arg)
@@ -979,14 +979,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_swi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
}
static bool trans_swx(DisasContext *dc, arg_typea *arg)
@@ -1015,7 +1015,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val,
reg_for_write(dc, arg->rd),
- dc->mem_index, MO_TEUL);
+ dc->mem_index, MO_TE | MO_UL);
tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail);
--
2.47.1
next prev parent reply other threads:[~2025-02-06 11:35 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-06 11:33 [PATCH v4 00/16] hw/microblaze: Allow running cross-endian vCPUs Philippe Mathieu-Daudé
2025-02-06 11:33 ` [PATCH v4 01/16] hw/intc/xilinx_intc: Make device endianness configurable Philippe Mathieu-Daudé
2025-02-06 11:33 ` [PATCH v4 02/16] hw/net/xilinx_ethlite: " Philippe Mathieu-Daudé
2025-02-06 11:33 ` [PATCH v4 03/16] hw/timer/xilinx_timer: " Philippe Mathieu-Daudé
2025-02-06 11:33 ` [PATCH v4 04/16] hw/char/xilinx_uartlite: " Philippe Mathieu-Daudé
2025-02-06 11:33 ` [PATCH v4 05/16] hw/ssi/xilinx_spi: " Philippe Mathieu-Daudé
2025-02-06 11:33 ` [PATCH v4 06/16] hw/arm/xlnx-zynqmp: Use &error_abort for programming errors Philippe Mathieu-Daudé
2025-02-06 11:33 ` Philippe Mathieu-Daudé [this message]
2025-02-06 11:33 ` [PATCH v4 08/16] target/microblaze: Set MO_TE once in do_load() / do_store() Philippe Mathieu-Daudé
2025-02-06 11:33 ` [PATCH v4 09/16] target/microblaze: Introduce mo_endian() helper Philippe Mathieu-Daudé
2025-02-06 11:33 ` [PATCH v4 10/16] target/microblaze: Consider endianness while translating code Philippe Mathieu-Daudé
2025-02-06 11:33 ` [PATCH v4 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines Philippe Mathieu-Daudé
2025-02-06 11:33 ` [PATCH v4 12/16] tests/functional: Explicit endianness of microblaze assets Philippe Mathieu-Daudé
2025-02-06 11:33 ` [PATCH v4 13/16] tests/functional: Allow microblaze tests to take a machine name argument Philippe Mathieu-Daudé
2025-02-06 12:36 ` Thomas Huth
2025-02-06 11:33 ` [PATCH v4 14/16] tests/functional: Have microblaze tests inherit common parent class Philippe Mathieu-Daudé
2025-02-06 12:41 ` Thomas Huth
2025-02-06 11:33 ` [PATCH v4 15/16] tests/functional: Move microblaze tests to " Philippe Mathieu-Daudé
2025-02-06 12:43 ` Thomas Huth
2025-02-06 11:33 ` [PATCH v4 16/16] tests/functional: Run cross-endian microblaze tests Philippe Mathieu-Daudé
2025-02-06 14:02 ` Thomas Huth
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