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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43907f19247sm58323555e9.1.2025.02.06.10.18.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 10:18:28 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , qemu-riscv@nongnu.org, Alistair Francis , Daniel Henrique Barboza , Bin Meng , Weiwei Li , Sunil V L , Liu Zhiwei , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 0/7] hw/riscv: Move few units to common_ss[] Date: Thu, 6 Feb 2025 19:18:20 +0100 Message-ID: <20250206181827.41557-1-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Remove target-specificity in some units and move them to the meson common_ss[] source set to build them once. Philippe Mathieu-Daudé (7): MAINTAINERS: Unify Alistair's professional email address target/riscv: Move target-agnostic definitions to 'cpu-qom.h' hw/riscv/opentitan: Include missing 'exec/address-spaces.h' header hw/riscv/boot: Use 'hwaddr' type for firmware addresses hw/riscv/iommu: Reduce needs for target-specific code hw/riscv/hart: Make 'riscv_hart.h' header target-agnostic hw/riscv: Move few objects to common_ss[] to build them once MAINTAINERS | 12 +++++----- include/hw/riscv/boot.h | 21 +++++++++-------- include/hw/riscv/boot_opensbi.h | 14 ++++++------ include/hw/riscv/riscv_hart.h | 4 ++-- target/riscv/cpu-qom.h | 40 +++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 24 -------------------- target/riscv/cpu_bits.h | 15 ------------- hw/riscv/boot.c | 28 +++++++++++------------ hw/riscv/opentitan.c | 1 + hw/riscv/riscv-iommu-pci.c | 5 +++-- hw/riscv/riscv-iommu-sys.c | 1 - hw/riscv/riscv-iommu.c | 1 + hw/riscv/virt-acpi-build.c | 1 + hw/riscv/meson.build | 5 +++-- 14 files changed, 88 insertions(+), 84 deletions(-) -- 2.47.1