All of lore.kernel.org
 help / color / mirror / Atom feed
From: Rob Herring <robh@kernel.org>
To: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Cc: Vinod Koul <vkoul@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Magnus Damm <magnus.damm@gmail.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	dmaengine@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 3/7] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
Date: Tue, 11 Feb 2025 16:26:30 -0600	[thread overview]
Message-ID: <20250211222630.GA1288508-robh@kernel.org> (raw)
In-Reply-To: <20250206220308.76669-4-fabrizio.castro.jz@renesas.com>

On Thu, Feb 06, 2025 at 10:03:04PM +0000, Fabrizio Castro wrote:
> Document the Renesas RZ/V2H(P) family of SoCs DMAC block.
> The Renesas RZ/V2H(P) DMAC is very similar to the one found on the
> Renesas RZ/G2L family of SoCs, but there are some differences:
> * It only uses one register area
> * It only uses one clock
> * It only uses one reset
> * Instead of using MID/IRD it uses REQ NO/ACK NO
> * It is connected to the Interrupt Control Unit (ICU)
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
>  .../bindings/dma/renesas,rz-dmac.yaml         | 152 +++++++++++++++---
>  1 file changed, 127 insertions(+), 25 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> index 82de3b927479..d4dd22432e49 100644
> --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> @@ -11,19 +11,23 @@ maintainers:
>  
>  properties:
>    compatible:
> -    items:
> -      - enum:
> -          - renesas,r7s72100-dmac # RZ/A1H
> -          - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
> -          - renesas,r9a07g044-dmac # RZ/G2{L,LC}
> -          - renesas,r9a07g054-dmac # RZ/V2L
> -          - renesas,r9a08g045-dmac # RZ/G3S
> -      - const: renesas,rz-dmac
> +    oneOf:
> +      - items:
> +          - enum:
> +              - renesas,r7s72100-dmac # RZ/A1H
> +              - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
> +              - renesas,r9a07g044-dmac # RZ/G2{L,LC}
> +              - renesas,r9a07g054-dmac # RZ/V2L
> +              - renesas,r9a08g045-dmac # RZ/G3S
> +          - const: renesas,rz-dmac
> +
> +      - const: renesas,r9a09g057-dmac # RZ/V2H(P)
>  
>    reg:
>      items:
>        - description: Control and channel register block
>        - description: DMA extended resource selector block
> +    minItems: 1
>  
>    interrupts:
>      maxItems: 17
> @@ -52,6 +56,7 @@ properties:
>      items:
>        - description: DMA main clock
>        - description: DMA register access clock
> +    minItems: 1
>  
>    clock-names:
>      items:
> @@ -61,14 +66,22 @@ properties:
>    '#dma-cells':
>      const: 1
>      description:
> -      The cell specifies the encoded MID/RID values of the DMAC port
> -      connected to the DMA client and the slave channel configuration
> -      parameters.
> +      For the RZ/A1H, RZ/Five, RZ/G2{L,LC,UL}, RZ/V2L, and RZ/G3S SoCs, the cell
> +      specifies the encoded MID/RID values of the DMAC port connected to the
> +      DMA client and the slave channel configuration parameters.
>        bits[0:9] - Specifies MID/RID value
>        bit[10] - Specifies DMA request high enable (HIEN)
>        bit[11] - Specifies DMA request detection type (LVL)
>        bits[12:14] - Specifies DMAACK output mode (AM)
>        bit[15] - Specifies Transfer Mode (TM)
> +      For the RZ/V2H(P) SoC the cell specifies the REQ NO, the ACK NO, and the
> +      slave channel configuration parameters.
> +      bits[0:9] - Specifies the REQ NO
> +      bits[10:16] - Specifies the ACK NO
> +      bit[17] - Specifies DMA request high enable (HIEN)
> +      bit[18] - Specifies DMA request detection type (LVL)
> +      bits[19:21] - Specifies DMAACK output mode (AM)
> +      bit[22] - Specifies Transfer Mode (TM)
>  
>    dma-channels:
>      const: 16
> @@ -80,12 +93,29 @@ properties:
>      items:
>        - description: Reset for DMA ARESETN reset terminal
>        - description: Reset for DMA RST_ASYNC reset terminal
> +    minItems: 1
>  
>    reset-names:
>      items:
>        - const: arst
>        - const: rst_async
>  
> +  renesas,icu:
> +    description:
> +      On the RZ/V2H(P) SoC configures the ICU to which the DMAC is connected to.
> +      It must contain the phandle to the ICU, and the index of the DMAC as seen
> +      from the ICU (e.g. parameter k from register ICU_DMkSELy).
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      - items:
> +          - description: phandle to the ICU node.
> +          - description: The DMAC index.
> +              4 for DMAC0
> +              0 for DMAC1
> +              1 for DMAC2
> +              2 for DMAC3
> +              3 for DMAC4
> +
>  required:
>    - compatible
>    - reg
> @@ -98,27 +128,62 @@ allOf:
>    - $ref: dma-controller.yaml#
>  
>    - if:
> -      not:
> -        properties:
> -          compatible:
> -            contains:
> -              enum:
> -                - renesas,r7s72100-dmac
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a09g057-dmac
>      then:
> +      properties:
> +        reg:
> +          maxItems: 1
> +        clocks:
> +          maxItems: 1
> +        resets:
> +          maxItems: 1
> +
> +        clock-names: false
> +        reset-names: false
> +
>        required:
>          - clocks
> -        - clock-names
>          - power-domains
> +        - renesas,icu
>          - resets
> -        - reset-names
>  
>      else:
> -      properties:
> -        clocks: false
> -        clock-names: false
> -        power-domains: false
> -        resets: false
> -        reset-names: false
> +      if:

Please try to avoid nesting if/then/else. Not sure that's easy or not 
here. This diff is hard to read.

> +        not:
> +          properties:
> +            compatible:
> +              contains:
> +                enum:
> +                  - renesas,r7s72100-dmac
> +      then:
> +        properties:
> +          reg:
> +            minItems: 2
> +          clocks:
> +            minItems: 2
> +          resets:
> +            minItems: 2
> +
> +          renesas,icu: false
> +
> +        required:
> +          - clocks
> +          - clock-names
> +          - power-domains
> +          - resets
> +          - reset-names
> +
> +      else:
> +        properties:
> +          clocks: false
> +          clock-names: false
> +          power-domains: false
> +          resets: false
> +          reset-names: false
> +          renesas,icu: false
>  
>  additionalProperties: false
>  
> @@ -164,3 +229,40 @@ examples:
>          #dma-cells = <1>;
>          dma-channels = <16>;
>      };
> +
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +    dmac0: dma-controller@11400000 {
> +        compatible = "renesas,r9a09g057-dmac";

Is this example really different enough from the others to need it? I 
would drop it.

Rob


  reply	other threads:[~2025-02-11 22:26 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-06 22:03 [PATCH 0/7] Add DMAC support to the RZ/V2H(P) Fabrizio Castro
2025-02-06 22:03 ` [PATCH 1/7] clk: renesas: r9a09g057: Add entries for the DMACs Fabrizio Castro
2025-02-06 22:03 ` [PATCH 2/7] dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1H Fabrizio Castro
2025-02-06 22:03 ` [PATCH 3/7] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs Fabrizio Castro
2025-02-11 22:26   ` Rob Herring [this message]
2025-02-12 18:27     ` Fabrizio Castro
2025-02-06 22:03 ` [PATCH 4/7] irqchip/renesas-rzv2h: Add rzv2h_icu_register_dma_req_ack Fabrizio Castro
2025-02-07  7:49   ` Thomas Gleixner
2025-02-07 16:27     ` Fabrizio Castro
2025-02-06 22:03 ` [PATCH 5/7] dmaengine: sh: rz-dmac: Allow for multiple DMACs Fabrizio Castro
2025-02-06 22:03 ` [PATCH 6/7] dmaengine: sh: rz-dmac: Add RZ/V2H(P) support Fabrizio Castro
2025-02-06 22:03 ` [PATCH 7/7] arm64: dts: renesas: r9a09g057: Add DMAC nodes Fabrizio Castro

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20250211222630.GA1288508-robh@kernel.org \
    --to=robh@kernel.org \
    --cc=biju.das.jz@bp.renesas.com \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=dmaengine@vger.kernel.org \
    --cc=fabrizio.castro.jz@renesas.com \
    --cc=geert+renesas@glider.be \
    --cc=krzk+dt@kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-renesas-soc@vger.kernel.org \
    --cc=magnus.damm@gmail.com \
    --cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
    --cc=vkoul@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.