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X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org From: Niravkumar L Rabara 1) Document the required clock-names property because the driver requests the clock by name and not the index. 2) Add required clock-names property to the nand node in device tree. Changes in v2: * Document clock-names property for Cadence NAND controller. link to v1: - https://lore.kernel.org/all/20250107084955.2750154-1-niravkumar.l.rabara@intel.com/ Niravkumar L Rabara (2): dt-bindings: mtd: cadence: document required clock-names arm64: dts: socfpga: agilex5: add clock-names property to nand node Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml | 8 +++++++- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 1 + 2 files changed, 8 insertions(+), 1 deletion(-) -- 2.25.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78B291F03C1; Wed, 12 Feb 2025 09:57:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739354267; cv=none; b=Sy6nPnrmL3/Mg5AR+AISeAlodtsffcqFFFs3XSDDPdfbjuPrfK3oqcjyWpbXvkaBRQUUqzSdBmmbV5bKZC/oA/ykus20uXomqYmGnuYbVuFFMJWchENGHpx+qNyZBJWZGFjNi2lVHNEdqMNgv7DPFpTzNrTCh+Gi6v6/zxzQqJY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739354267; c=relaxed/simple; bh=RfajstfpTGLNdRrMN2hNwqxhrI3a/671OeateMPFz/E=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=ULPk6L+h9L8sAtlnRdmWpItX/OdBvqEhx6L2XNuDeptFM+nzwegnyc8LpD55y+bQcPaSSNWPPE59Inq/IzrXmrxUnE5JoLvF7zzoUjkxu9Dwj4WS4kBta0f4+aDjqKuTyYAFJXFc356QfuaquNxr/8TCLWr2c/v1eGM5gLQE6zE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=KOCOECGc; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="KOCOECGc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739354266; x=1770890266; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=RfajstfpTGLNdRrMN2hNwqxhrI3a/671OeateMPFz/E=; b=KOCOECGcp6DTePYDYwhxSj7ABlEUoqxCAjgc8vFoFWqMP/KRl/nifIAD QYX4IwAWim2PANdNazKM1JY61njvfq06UDaKpR0pKy19WntOuE88Pn/rK 9znpNrW7PRNDud7FMdcEoL07D3g7akjYtBV8a1fu4rJUChZutBGRNWrrd cUqi8FjOeOWq/hILu3PEGmVHpb9qF4zqT+oCR0OORvi1WwN85/XxsDhVz 8lI4zAPWUYjgLQuf3MKW3J4fYTMPUVGXl9kIe57rpJ/0dpBvZZ3UO6wD4 Roq37q66WiImbE+TFTtOlyDnJNLzEYhiBsIvjTVCIUaDmMcLSMGKBdlXB g==; X-CSE-ConnectionGUID: mkDEAnRiTeemPcnUklqKnw== X-CSE-MsgGUID: qaRMoVerTxSeESDK9ZqOxA== X-IronPort-AV: E=McAfee;i="6700,10204,11342"; a="50224532" X-IronPort-AV: E=Sophos;i="6.13,279,1732608000"; d="scan'208";a="50224532" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Feb 2025 01:57:45 -0800 X-CSE-ConnectionGUID: 7qg0NH+vTo2+M9Vz4tKZOA== X-CSE-MsgGUID: wzou7DIlTqS+ykPjuGYoeA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="112632043" Received: from pg15swiplab1181.png.altera.com ([10.244.232.167]) by orviesa010.jf.intel.com with ESMTP; 12 Feb 2025 01:57:41 -0800 From: niravkumar.l.rabara@intel.com To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Niravkumar L Rabara , nirav.rabara@altera.com, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/2] add clock-names property to nand node Date: Wed, 12 Feb 2025 17:54:05 +0800 Message-Id: <20250212095407.2667743-1-niravkumar.l.rabara@intel.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Niravkumar L Rabara 1) Document the required clock-names property because the driver requests the clock by name and not the index. 2) Add required clock-names property to the nand node in device tree. Changes in v2: * Document clock-names property for Cadence NAND controller. link to v1: - https://lore.kernel.org/all/20250107084955.2750154-1-niravkumar.l.rabara@intel.com/ Niravkumar L Rabara (2): dt-bindings: mtd: cadence: document required clock-names arm64: dts: socfpga: agilex5: add clock-names property to nand node Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml | 8 +++++++- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 1 + 2 files changed, 8 insertions(+), 1 deletion(-) -- 2.25.1