From: Peng Fan <peng.fan@oss.nxp.com>
To: Alexander Stein <alexander.stein@ew.tq-group.com>
Cc: Abel Vesa <abelvesa@kernel.org>, Peng Fan <peng.fan@nxp.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
linux-clk@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH 1/3] clk: imx: clk-fracn-gppll: Do not access num/denom register for integer PLL
Date: Fri, 14 Feb 2025 12:29:44 +0800 [thread overview]
Message-ID: <20250214042944.GD20275@localhost.localdomain> (raw)
In-Reply-To: <20250210160012.783446-1-alexander.stein@ew.tq-group.com>
On Mon, Feb 10, 2025 at 05:00:09PM +0100, Alexander Stein wrote:
>Similar to clk_fracn_gppll_set_rate(), do not access the numerator and
>denominator register for integer PLL. Set MFD/MFN to 0 instead, so the
>table lookup will match.
For integer, the calculation will not take mfn/mfi into consideration.
Do you see this in test or just code inspection?
>See i.MX93 RM section 74.5.2.1 (PLL memory map) for ARMPLL, addresses
>0x40 and 0x50 are not listed/reserved.
>
>Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
>---
> drivers/clk/imx/clk-fracn-gppll.c | 17 ++++++++++++-----
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
>diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
>index 85771afd4698a..3aef548110e25 100644
>--- a/drivers/clk/imx/clk-fracn-gppll.c
>+++ b/drivers/clk/imx/clk-fracn-gppll.c
>@@ -154,17 +154,24 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon
> {
> struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
> const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
>- u32 pll_numerator, pll_denominator, pll_div;
>+ u32 pll_div;
> u32 mfi, mfn, mfd, rdiv, odiv;
> u64 fvco = parent_rate;
> long rate = 0;
> int i;
>
>- pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR);
>- mfn = FIELD_GET(PLL_MFN_MASK, pll_numerator);
>+ if (pll->flags & CLK_FRACN_GPPLL_FRACN) {
>+ u32 pll_numerator, pll_denominator;
>+
>+ pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR);
>+ mfn = FIELD_GET(PLL_MFN_MASK, pll_numerator);
>
>- pll_denominator = readl_relaxed(pll->base + PLL_DENOMINATOR);
>- mfd = FIELD_GET(PLL_MFD_MASK, pll_denominator);
>+ pll_denominator = readl_relaxed(pll->base + PLL_DENOMINATOR);
>+ mfd = FIELD_GET(PLL_MFD_MASK, pll_denominator);
>+ } else {
>+ mfd = 0;
>+ mfn = 0;
>+ }
Reading the registers for ARM PLL, should be 0 even RM not list.
But it is good that using a check here. So I am ok with this change.
Regards,
Peng
>
> pll_div = readl_relaxed(pll->base + PLL_DIV);
> mfi = FIELD_GET(PLL_MFI_MASK, pll_div);
>--
>2.34.1
>
prev parent reply other threads:[~2025-02-14 3:22 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-10 16:00 [RFC PATCH 1/3] clk: imx: clk-fracn-gppll: Do not access num/denom register for integer PLL Alexander Stein
2025-02-10 16:00 ` [RFC PATCH 2/3] clk: imx: clk-fracn-gppll: Refactor clk_fracn_gppll_calc_rate Alexander Stein
2025-02-10 16:00 ` [RFC PATCH 3/3] clk: imx: clk-fracn-gppll: Support dynamic rates Alexander Stein
2025-02-11 7:47 ` Sascha Hauer
2025-02-14 4:45 ` Peng Fan
2025-02-14 4:29 ` Peng Fan [this message]
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