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From: Mario Limonciello <superm1@kernel.org>
To: "Gautham R . Shenoy" <gautham.shenoy@amd.com>,
	Perry Yuan <perry.yuan@amd.com>
Cc: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>,
	linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT
	AND 64-BIT)),
	linux-pm@vger.kernel.org (open list:CPU FREQUENCY SCALING
	FRAMEWORK), Mario Limonciello <mario.limonciello@amd.com>,
	Dhananjay Ugwekar <dhananjay.ugwekar@amd.com>
Subject: [PATCH v2 11/17] cpufreq/amd-pstate: Replace all AMD_CPPC_* macros with masks
Date: Fri, 14 Feb 2025 18:52:38 -0600	[thread overview]
Message-ID: <20250215005244.1212285-12-superm1@kernel.org> (raw)
In-Reply-To: <20250215005244.1212285-1-superm1@kernel.org>

From: Mario Limonciello <mario.limonciello@amd.com>

Bitfield masks are easier to follow and less error prone.

Reviewed-by: Dhananjay Ugwekar <dhananjay.ugwekar@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
v2:
 * Add a comment in msr-index.h
 * Pick up tag
---
 arch/x86/include/asm/msr-index.h | 20 +++++++++++---------
 arch/x86/kernel/acpi/cppc.c      |  2 +-
 drivers/cpufreq/amd-pstate-ut.c  |  8 ++++----
 drivers/cpufreq/amd-pstate.c     | 16 ++++++----------
 4 files changed, 22 insertions(+), 24 deletions(-)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 3eadc4d5de837..4bb87884998a0 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -700,15 +700,17 @@
 #define MSR_AMD_CPPC_REQ		0xc00102b3
 #define MSR_AMD_CPPC_STATUS		0xc00102b4
 
-#define AMD_CPPC_LOWEST_PERF(x)		(((x) >> 0) & 0xff)
-#define AMD_CPPC_LOWNONLIN_PERF(x)	(((x) >> 8) & 0xff)
-#define AMD_CPPC_NOMINAL_PERF(x)	(((x) >> 16) & 0xff)
-#define AMD_CPPC_HIGHEST_PERF(x)	(((x) >> 24) & 0xff)
-
-#define AMD_CPPC_MAX_PERF(x)		(((x) & 0xff) << 0)
-#define AMD_CPPC_MIN_PERF(x)		(((x) & 0xff) << 8)
-#define AMD_CPPC_DES_PERF(x)		(((x) & 0xff) << 16)
-#define AMD_CPPC_ENERGY_PERF_PREF(x)	(((x) & 0xff) << 24)
+/* Masks for use with MSR_AMD_CPPC_CAP1 */
+#define AMD_CPPC_LOWEST_PERF_MASK	GENMASK(7, 0)
+#define AMD_CPPC_LOWNONLIN_PERF_MASK	GENMASK(15, 8)
+#define AMD_CPPC_NOMINAL_PERF_MASK	GENMASK(23, 16)
+#define AMD_CPPC_HIGHEST_PERF_MASK	GENMASK(31, 24)
+
+/* Masks for use with MSR_AMD_CPPC_REQ */
+#define AMD_CPPC_MAX_PERF_MASK		GENMASK(7, 0)
+#define AMD_CPPC_MIN_PERF_MASK		GENMASK(15, 8)
+#define AMD_CPPC_DES_PERF_MASK		GENMASK(23, 16)
+#define AMD_CPPC_EPP_PERF_MASK		GENMASK(31, 24)
 
 /* AMD Performance Counter Global Status and Control MSRs */
 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS	0xc0000300
diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c
index f96053c305c61..77bfb846490c0 100644
--- a/arch/x86/kernel/acpi/cppc.c
+++ b/arch/x86/kernel/acpi/cppc.c
@@ -151,7 +151,7 @@ int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf)
 		if (ret)
 			goto out;
 
-		val = AMD_CPPC_HIGHEST_PERF(val);
+		val = FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, val);
 	} else {
 		ret = cppc_get_highest_perf(cpu, &val);
 		if (ret)
diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-ut.c
index 9db20ac357042..067e9e325102e 100644
--- a/drivers/cpufreq/amd-pstate-ut.c
+++ b/drivers/cpufreq/amd-pstate-ut.c
@@ -142,10 +142,10 @@ static int amd_pstate_ut_check_perf(u32 index)
 				return ret;
 			}
 
-			highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
-			nominal_perf = AMD_CPPC_NOMINAL_PERF(cap1);
-			lowest_nonlinear_perf = AMD_CPPC_LOWNONLIN_PERF(cap1);
-			lowest_perf = AMD_CPPC_LOWEST_PERF(cap1);
+			highest_perf = FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, cap1);
+			nominal_perf = FIELD_GET(AMD_CPPC_NOMINAL_PERF_MASK, cap1);
+			lowest_nonlinear_perf = FIELD_GET(AMD_CPPC_LOWNONLIN_PERF_MASK, cap1);
+			lowest_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
 		}
 
 		cur_perf = READ_ONCE(cpudata->perf);
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index e5983e5c77ba2..0a7e69fd32dbf 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -89,11 +89,6 @@ static bool cppc_enabled;
 static bool amd_pstate_prefcore = true;
 static struct quirk_entry *quirks;
 
-#define AMD_CPPC_MAX_PERF_MASK		GENMASK(7, 0)
-#define AMD_CPPC_MIN_PERF_MASK		GENMASK(15, 8)
-#define AMD_CPPC_DES_PERF_MASK		GENMASK(23, 16)
-#define AMD_CPPC_EPP_PERF_MASK		GENMASK(31, 24)
-
 /*
  * AMD Energy Preference Performance (EPP)
  * The EPP is used in the CCLK DPM controller to drive
@@ -439,12 +434,13 @@ static int msr_init_perf(struct amd_cpudata *cpudata)
 
 	perf.highest_perf = numerator;
 	perf.max_limit_perf = numerator;
-	perf.min_limit_perf = AMD_CPPC_LOWEST_PERF(cap1);
-	perf.nominal_perf = AMD_CPPC_NOMINAL_PERF(cap1);
-	perf.lowest_nonlinear_perf = AMD_CPPC_LOWNONLIN_PERF(cap1);
-	perf.lowest_perf = AMD_CPPC_LOWEST_PERF(cap1);
+	perf.min_limit_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
+	perf.nominal_perf = FIELD_GET(AMD_CPPC_NOMINAL_PERF_MASK, cap1);
+	perf.lowest_nonlinear_perf = FIELD_GET(AMD_CPPC_LOWNONLIN_PERF_MASK, cap1);
+	perf.lowest_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
 	WRITE_ONCE(cpudata->perf, perf);
-	WRITE_ONCE(cpudata->prefcore_ranking, AMD_CPPC_HIGHEST_PERF(cap1));
+	WRITE_ONCE(cpudata->prefcore_ranking, FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, cap1));
+
 	return 0;
 }
 
-- 
2.43.0


  parent reply	other threads:[~2025-02-15  0:53 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-15  0:52 [PATCH v2 00/17] amd-pstate cleanups Mario Limonciello
2025-02-15  0:52 ` [PATCH v2 01/17] cpufreq/amd-pstate: Show a warning when a CPU fails to setup Mario Limonciello
2025-02-17  5:53   ` Gautham R. Shenoy
2025-02-15  0:52 ` [PATCH v2 02/17] cpufreq/amd-pstate: Drop min and max cached frequencies Mario Limonciello
2025-02-17  6:38   ` Gautham R. Shenoy
2025-02-17 21:06     ` Mario Limonciello
2025-02-15  0:52 ` [PATCH v2 03/17] cpufreq/amd-pstate: Move perf values into a union Mario Limonciello
2025-02-17  9:01   ` Gautham R. Shenoy
2025-02-15  0:52 ` [PATCH v2 04/17] cpufreq/amd-pstate: Overhaul locking Mario Limonciello
2025-02-17  9:12   ` Gautham R. Shenoy
2025-02-15  0:52 ` [PATCH v2 05/17] cpufreq/amd-pstate: Drop `cppc_cap1_cached` Mario Limonciello
2025-02-17  9:12   ` Gautham R. Shenoy
2025-02-15  0:52 ` [PATCH v2 06/17] cpufreq/amd-pstate-ut: Use _free macro to free put policy Mario Limonciello
2025-02-17 10:11   ` Gautham R. Shenoy
2025-02-15  0:52 ` [PATCH v2 07/17] cpufreq/amd-pstate-ut: Allow lowest nonlinear and lowest to be the same Mario Limonciello
2025-02-17 10:14   ` Gautham R. Shenoy
2025-02-15  0:52 ` [PATCH v2 08/17] cpufreq/amd-pstate-ut: Drop SUCCESS and FAIL enums Mario Limonciello
2025-02-17 11:34   ` Gautham R. Shenoy
2025-02-15  0:52 ` [PATCH v2 09/17] cpufreq/amd-pstate-ut: Continue on missing policies Mario Limonciello
2025-02-17 11:38   ` Gautham R. Shenoy
2025-02-17 17:04     ` Mario Limonciello
2025-02-15  0:52 ` [PATCH v2 10/17] cpufreq/amd-pstate-ut: Adjust variable scope for amd_pstate_ut_check_freq() Mario Limonciello
2025-02-17 11:39   ` Gautham R. Shenoy
2025-02-15  0:52 ` Mario Limonciello [this message]
2025-02-17 13:48   ` [PATCH v2 11/17] cpufreq/amd-pstate: Replace all AMD_CPPC_* macros with masks Gautham R. Shenoy
2025-02-17 17:12   ` kernel test robot
2025-02-15  0:52 ` [PATCH v2 12/17] cpufreq/amd-pstate: Cache CPPC request in shared mem case too Mario Limonciello
2025-02-17 13:54   ` Gautham R. Shenoy
2025-02-15  0:52 ` [PATCH v2 13/17] cpufreq/amd-pstate: Move all EPP tracing into *_update_perf and *_set_epp functions Mario Limonciello
2025-02-17 14:14   ` Gautham R. Shenoy
2025-02-15  0:52 ` [PATCH v2 14/17] cpufreq/amd-pstate: Update cppc_req_cached for shared mem EPP writes Mario Limonciello
2025-02-17 14:30   ` Gautham R. Shenoy
2025-02-15  0:52 ` [PATCH v2 15/17] cpufreq/amd-pstate: Drop debug statements for policy setting Mario Limonciello
2025-02-17 14:31   ` Gautham R. Shenoy
2025-02-15  0:52 ` [PATCH v2 16/17] cpufreq/amd-pstate: Rework CPPC enabling Mario Limonciello
2025-02-15  0:52 ` [PATCH v2 17/17] cpufreq/amd-pstate: Stop caching EPP Mario Limonciello

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