From: kernel test robot <lkp@intel.com>
Cc: oe-kbuild-all@lists.linux.dev
Subject: [intel-lts:pr/57 1/1] arch/riscv/kernel/smp.c:98: Error: unrecognized opcode `csrc 0x144,2', extension `zicsr' required
Date: Thu, 20 Feb 2025 13:02:30 +0800 [thread overview]
Message-ID: <202502201325.6ZRDoyGS-lkp@intel.com> (raw)
tree: https://github.com/intel/linux-intel-lts.git pr/57
head: 6fe7458ff80d33a5dba8b386c88d33ffd2ccb47d
commit: a3182c91ef4e7dda90ff080a4132efd3ecb8786a [1/1] RISC-V: Access CSRs using CSR numbers
config: riscv-rv32_defconfig (https://download.01.org/0day-ci/archive/20250220/202502201325.6ZRDoyGS-lkp@intel.com/config)
compiler: riscv32-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250220/202502201325.6ZRDoyGS-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202502201325.6ZRDoyGS-lkp@intel.com/
All errors (new ones prefixed by >>):
arch/riscv/kernel/smp.c:74:6: warning: no previous prototype for 'arch_match_cpu_phys_id' [-Wmissing-prototypes]
74 | bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
| ^~~~~~~~~~~~~~~~~~~~~~
arch/riscv/kernel/smp.c:80:5: warning: no previous prototype for 'setup_profiling_timer' [-Wmissing-prototypes]
80 | int setup_profiling_timer(unsigned int multiplier)
| ^~~~~~~~~~~~~~~~~~~~~
arch/riscv/kernel/smp.c: Assembler messages:
>> arch/riscv/kernel/smp.c:98: Error: unrecognized opcode `csrc 0x144,2', extension `zicsr' required
arch/riscv/include/asm/cacheflush.h:25: Error: unrecognized opcode `fence.i', extension `zifencei' required
--
arch/riscv/include/asm/irqflags.h: Assembler messages:
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc a4,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc a4,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,a4', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc a3,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,a3', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode `csrs 0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode `csrs 0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc a4,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,a4', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode `csrs 0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc a3,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,a4', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc a1,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,a2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode `csrs 0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode `csrs 0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode `csrs 0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode `csrs 0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode `csrs 0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode `csrs 0x100,2', extension `zicsr' required
>> arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc a4,0x100,a4', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,a4', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode `csrs 0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode `csrs 0x100,2', extension `zicsr' required
--
arch/riscv/include/asm/irqflags.h: Assembler messages:
arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode `csrs 0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:36: Error: unrecognized opcode `csrc 0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:36: Error: unrecognized opcode `csrc 0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc a2,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,a2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc s6,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,s6', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,a2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc s1,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,s1', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc s3,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,s3', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:36: Error: unrecognized opcode `csrc 0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode `csrs 0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode `csrs 0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode `csrs 0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc a0,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,t3', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,t3', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc s4,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,s4', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc a0,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,t3', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,t3', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc s4,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,s4', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc a5,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,a5', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,a5', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc t3,0x100,2', extension `zicsr' required
>> arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,t0', extension `zicsr' required
>> arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,t0', extension `zicsr' required
>> arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc t4,0x100,2', extension `zicsr' required
>> arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,t4', extension `zicsr' required
>> arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,t4', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc t3,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,t3', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,t3', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:24: Error: unrecognized opcode `csrr a5,0x100', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode `csrs 0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc a0,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,t3', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,t3', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:42: Error: unrecognized opcode `csrrc s4,0x100,2', extension `zicsr' required
arch/riscv/include/asm/irqflags.h:60: Error: unrecognized opcode `csrs 0x100,s4', extension `zicsr' required
vim +98 arch/riscv/kernel/smp.c
73
> 74 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
75 {
76 return phys_id == cpuid_to_hartid_map(cpu);
77 }
78
79 /* Unsupported */
80 int setup_profiling_timer(unsigned int multiplier)
81 {
82 return -EINVAL;
83 }
84
85 static void ipi_stop(void)
86 {
87 set_cpu_online(smp_processor_id(), false);
88 while (1)
89 wait_for_interrupt();
90 }
91
92 void riscv_software_interrupt(void)
93 {
94 unsigned long *pending_ipis = &ipi_data[smp_processor_id()].bits;
95 unsigned long *stats = ipi_data[smp_processor_id()].stats;
96
97 /* Clear pending IPI */
> 98 csr_clear(CSR_SIP, SIE_SSIE);
99
100 while (true) {
101 unsigned long ops;
102
103 /* Order bit clearing and data access. */
104 mb();
105
106 ops = xchg(pending_ipis, 0);
107 if (ops == 0)
108 return;
109
110 if (ops & (1 << IPI_RESCHEDULE)) {
111 stats[IPI_RESCHEDULE]++;
112 scheduler_ipi();
113 }
114
115 if (ops & (1 << IPI_CALL_FUNC)) {
116 stats[IPI_CALL_FUNC]++;
117 generic_smp_call_function_interrupt();
118 }
119
120 if (ops & (1 << IPI_CPU_STOP)) {
121 stats[IPI_CPU_STOP]++;
122 ipi_stop();
123 }
124
125 BUG_ON((ops >> IPI_MAX) != 0);
126
127 /* Order data access and bit testing. */
128 mb();
129 }
130 }
131
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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