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Fri, 21 Feb 2025 04:44:28 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::766e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f69b3ca41sm3640123f8f.27.2025.02.21.04.44.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 04:44:27 -0800 (PST) Date: Fri, 21 Feb 2025 13:44:27 +0100 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH v2 2/3] target/riscv/kvm: add kvm_riscv_reset_regs_csr() Message-ID: <20250221-94f103225a50973887399620@orel> References: <20250221122623.495188-1-dbarboza@ventanamicro.com> <20250221122623.495188-3-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250221122623.495188-3-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Fri, Feb 21, 2025 at 09:26:22AM -0300, Daniel Henrique Barboza wrote: > We're setting reset vals for KVM csrs during kvm_riscv_reset_vcpu(), but > in no particular order and missing some of them (like env->mstatus). > > Create a helper to do that, unclogging reset_vcpu(), and initialize > env->mstatus as well. Keep the regs in the same order they appear in > struct kvm_riscv_csr from the KVM UAPI, similar to what > kvm_riscv_(get|put)_regs_csr are doing. This will make a bit easier to > add new KVM CSRs and to verify which values we're writing back to KVM > during vcpu reset. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/kvm/kvm-cpu.c | 23 +++++++++++++++-------- > 1 file changed, 15 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c > index 484b6afe7c..f14fcc58bb 100644 > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -605,6 +605,19 @@ static int kvm_riscv_put_regs_core(CPUState *cs) > return ret; > } > > +static void kvm_riscv_reset_regs_csr(CPURISCVState *env) > +{ > + env->mstatus = 0; > + env->mie = 0; > + env->stvec = 0; > + env->sscratch = 0; > + env->sepc = 0; > + env->scause = 0; > + env->stval = 0; > + env->mip = 0; > + env->satp = 0; > +} > + > static int kvm_riscv_get_regs_csr(CPUState *cs) > { > CPURISCVState *env = &RISCV_CPU(cs)->env; > @@ -1609,14 +1622,8 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu) > env->pc = cpu->env.kernel_addr; > env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ > env->gpr[11] = cpu->env.fdt_addr; /* a1 */ > - env->satp = 0; > - env->mie = 0; > - env->stvec = 0; > - env->sscratch = 0; > - env->sepc = 0; > - env->scause = 0; > - env->stval = 0; > - env->mip = 0; > + > + kvm_riscv_reset_regs_csr(env); > } > > void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) > -- > 2.48.1 > Reviewed-by: Andrew Jones