From: "Krzysztof Wilczyński" <kw@linux.com>
To: Zhiyuan Dai <daizhiyuan@phytium.com.cn>
Cc: helgaas@kernel.org, bhelgaas@google.com,
christian.koenig@amd.com, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: Re: [PATCH v3] PCI: Update Resizable BAR Capability Register fields
Date: Fri, 21 Feb 2025 10:21:01 +0900 [thread overview]
Message-ID: <20250221012101.GF2510987@rocinante> (raw)
In-Reply-To: <20250220012546.318577-1-daizhiyuan@phytium.com.cn>
Hello,
> PCI Express Base Spec r6.0 defines BAR size up to 8 EB (2^63 bytes),
> but supporting anything bigger than 128TB requires changes to pci_rebar_get_possible_sizes()
> to read the additional Capability bits from the Control register.
>
> If 8EB support is required, callers will need to be updated to handle u64 instead of u32.
> For now, support is limited to 128TB, and support for sizes greater than 128TB can be
> deferred to a later time.
I think this would be a v4?
If the reviews still stand, then we can correct the subject line while
applying the patch. No need to send another e-mail.
Krzysztof
next prev parent reply other threads:[~2025-02-21 1:21 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-18 6:40 [PATCH] PCI: Update Resizable BAR Capability Register fields Zhiyuan Dai
2025-02-18 20:25 ` Bjorn Helgaas
2025-02-19 2:27 ` [PATCH v2] " Zhiyuan Dai
2025-02-19 18:34 ` Bjorn Helgaas
2025-02-20 1:25 ` [PATCH v3] " Zhiyuan Dai
2025-02-21 1:21 ` Krzysztof Wilczyński [this message]
2025-02-21 22:35 ` Bjorn Helgaas
2025-02-20 1:30 ` Zhiyuan Dai
2025-02-20 9:18 ` Christian König
2025-02-20 12:42 ` Niklas Cassel
2025-02-21 1:09 ` Zhiyuan Dai
2025-03-06 11:34 ` Ilpo Järvinen
2025-03-07 5:35 ` [PATCH v4] " Zhiyuan Dai
2025-03-07 17:32 ` Bjorn Helgaas
2025-03-11 1:11 ` Zhiyuan Dai
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