From: "Michael S. Tsirkin" <mst@redhat.com>
To: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"jasowang@redhat.com" <jasowang@redhat.com>,
"zhenzhong.duan@intel.com" <zhenzhong.duan@intel.com>,
"kevin.tian@intel.com" <kevin.tian@intel.com>,
"yi.l.liu@intel.com" <yi.l.liu@intel.com>,
"joao.m.martins@oracle.com" <joao.m.martins@oracle.com>,
"peterx@redhat.com" <peterx@redhat.com>,
"tjeznach@rivosinc.com" <tjeznach@rivosinc.com>,
"minwoo.im@samsung.com" <minwoo.im@samsung.com>
Subject: Re: [PATCH v3 00/19] intel_iommu: Add ATS support
Date: Fri, 21 Feb 2025 05:57:11 -0500 [thread overview]
Message-ID: <20250221055659-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <20250221080331.186285-1-clement.mathieu--drif@eviden.com>
On Fri, Feb 21, 2025 at 08:07:25AM +0000, CLEMENT MATHIEU--DRIF wrote:
> From: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com>
>
> This patch set belongs to a list of series that add SVM support for VT-d.
>
> Here we focus on implementing ATS support in the IOMMU and adding a
> PCI-level API to be used by virtual devices.
>
> This work is based on the VT-d specification version 4.1 (March 2023).
>
> Here is a link to our GitHub repository where you can find the following elements:
> - Qemu with all the patches for SVM
> - ATS
> - PRI
> - Device IOTLB invalidations
> - Requests with already pre-translated addresses
> - A demo device
> - A simple driver for the demo device
> - A userspace program (for testing and demonstration purposes)
>
> https://github.com/BullSequana/Qemu-in-guest-SVM-demo
more build failures:
https://gitlab.com/mstredhat/qemu/-/jobs/9206060668
> ===============
>
> Context and design notes
> ''''''''''''''''''''''''
>
> The main purpose of this work is to enable vVT-d users to make
> translation requests to the vIOMMU as described in the PCIe Gen 5.0
> specification (section 10). Moreover, we aim to implement a
> PCI/Memory-level framework that could be used by other vIOMMUs
> to implement the same features.
>
> What is ATS?
> ''''''''''''
>
> ATS (Address Translation Service) is a PCIe-level protocol that
> enables PCIe devices to query an IOMMU for virtual to physical
> address translations in a specific address space (such as a userland
> process address space). When a device receives translation responses
> from an IOMMU, it may decide to store them in an internal cache,
> often known as "ATC" (Address Translation Cache) or "Device IOTLB".
> To keep page tables and caches consistent, the IOMMU is allowed to
> send asynchronous invalidation requests to its client devices.
>
> To avoid introducing an unnecessarily complex API, this series simply
> exposes 3 functions. The first 2 are a pair of setup functions that
> are called to install and remove the ATS invalidation callback during
> the initialization phase of a process. The third one will be
> used to request translations. The callback setup API introduced in
> this series calls the IOMMUNotifier API under the hood.
>
> API design
> ''''''''''
>
> - int pci_register_iommu_tlb_event_notifier(PCIDevice *dev,
> uint32_t pasid,
> IOMMUNotifier *n);
>
> - int pci_unregister_iommu_tlb_event_notifier(PCIDevice *dev, uint32_t pasid,
> IOMMUNotifier *n);
>
> - ssize_t pci_ats_request_translation_pasid(PCIDevice *dev, uint32_t pasid,
> bool priv_req, bool exec_req,
> hwaddr addr, size_t length,
> bool no_write,
> IOMMUTLBEntry *result,
> size_t result_length,
> uint32_t *err_count);
>
> Although device developers may want to implement custom ATC for
> testing or performance measurement purposes, we provide a generic
> implementation as a utility module.
>
> Overview
> ''''''''
>
> Here are the interactions between an ATS-capable PCIe device and the vVT-d:
>
>
>
> ┌───────────┐ ┌────────────┐
> │Device │ │PCI / Memory│
> │ │ pci_ats_request_│abstraction │ iommu_ats_
> │ │ translation_ │ │ request_
> │┌─────────┐│ pasid │ AS lookup │ translation
> ││Logic ││────────────────>│╶╶╶╶╶╶╶╶╶╶╶>│──────┐
> │└─────────┘│<────────────────│<╶╶╶╶╶╶╶╶╶╶╶│<──┐ │
> │┌─────────┐│ │ │ │ │
> ││inv func ││<───────┐ │ │ │ │
> │└─────────┘│ │ │ │ │ │
> │ │ │ │ │ │ │ │
> │ ∨ │ │ │ │ │ │
> │┌─────────┐│ │ │ │ │ │
> ││ATC ││ │ │ │ │ │
> │└─────────┘│ │ │ │ │ │
> └───────────┘ │ └────────────┘ │ │
> │ │ │
> │ │ │
> │ │ │
> │ │ │
> │ ┌────────────────────┼──┼─┐
> │ │vVT-d │ │ │
> │ │ │ │ │
> │ │ │ │ │
> │ │ │ │ │
> │ │ │ │ │
> │ │ │ ∨ │
> │ │┌───────────────────────┐│
> │ ││Translation logic ││
> │ │└───────────────────────┘│
> └────┼────────────┐ │
> │ │ │
> │┌───────────────────────┐│
> ││ Invalidation queue ││
> │└───────────∧───────────┘│
> └────────────┼────────────┘
> │
> │
> │
> ┌────────────────────────┐
> │Kernel driver │
> │ │
> └────────────────────────┘
>
> v3
> - Rebase onto master
> - Fix compilation issue in non-debug mode (Michael)
>
> v2
> - Rebase on master after merge of Zhenzhong's FLTS series
> - Rename the series as it is now based on master.
>
> - Changes after review by Michael:
> - Split long lines in memory.h
> - Change patch encoding (no UTF-8)
>
> - Changes after review by Zhenzhong:
> - Rework "Fill the PASID field when creating an IOMMUTLBEntry"
>
>
>
> Clement Mathieu--Drif (19):
> memory: Add permissions in IOMMUAccessFlags
> intel_iommu: Declare supported PASID size
> memory: Allow to store the PASID in IOMMUTLBEntry
> intel_iommu: Fill the PASID field when creating an IOMMUTLBEntry
> pcie: Add helper to declare PASID capability for a pcie device
> pcie: Helper functions to check if PASID is enabled
> pcie: Helper function to check if ATS is enabled
> pci: Cache the bus mastering status in the device
> pci: Add IOMMU operations to get memory regions with PASID
> intel_iommu: Implement the get_memory_region_pasid iommu operation
> memory: Store user data pointer in the IOMMU notifiers
> pci: Add a pci-level initialization function for iommu notifiers
> atc: Generic ATC that can be used by PCIe devices that support SVM
> atc: Add unit tests
> memory: Add an API for ATS support
> pci: Add a pci-level API for ATS
> intel_iommu: Set address mask when a translation fails and adjust W
> permission
> intel_iommu: Return page walk level even when the translation fails
> intel_iommu: Add support for ATS
>
> hw/i386/intel_iommu.c | 125 ++++++--
> hw/i386/intel_iommu_internal.h | 2 +
> hw/pci/pci.c | 111 ++++++-
> hw/pci/pcie.c | 42 +++
> include/exec/memory.h | 51 +++-
> include/hw/i386/intel_iommu.h | 2 +-
> include/hw/pci/pci.h | 83 ++++++
> include/hw/pci/pci_device.h | 1 +
> include/hw/pci/pcie.h | 9 +-
> include/hw/pci/pcie_regs.h | 5 +
> system/memory.c | 21 ++
> tests/unit/meson.build | 1 +
> tests/unit/test-atc.c | 527 +++++++++++++++++++++++++++++++++
> util/atc.c | 211 +++++++++++++
> util/atc.h | 117 ++++++++
> util/meson.build | 1 +
> 16 files changed, 1278 insertions(+), 31 deletions(-)
> create mode 100644 tests/unit/test-atc.c
> create mode 100644 util/atc.c
> create mode 100644 util/atc.h
>
> --
> 2.48.1
next prev parent reply other threads:[~2025-02-21 10:58 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-21 8:07 [PATCH v3 00/19] intel_iommu: Add ATS support CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 01/19] memory: Add permissions in IOMMUAccessFlags CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 02/19] intel_iommu: Declare supported PASID size CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 03/19] memory: Allow to store the PASID in IOMMUTLBEntry CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 04/19] intel_iommu: Fill the PASID field when creating an IOMMUTLBEntry CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 05/19] pcie: Add helper to declare PASID capability for a pcie device CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 06/19] pcie: Helper functions to check if PASID is enabled CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 07/19] pcie: Helper function to check if ATS " CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 08/19] pci: Cache the bus mastering status in the device CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 09/19] pci: Add IOMMU operations to get memory regions with PASID CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 10/19] intel_iommu: Implement the get_memory_region_pasid iommu operation CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 11/19] memory: Store user data pointer in the IOMMU notifiers CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 13/19] atc: Generic ATC that can be used by PCIe devices that support SVM CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 12/19] pci: Add a pci-level initialization function for iommu notifiers CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 14/19] atc: Add unit tests CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 15/19] memory: Add an API for ATS support CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 17/19] intel_iommu: Set address mask when a translation fails and adjust W permission CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 16/19] pci: Add a pci-level API for ATS CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 18/19] intel_iommu: Return page walk level even when the translation fails CLEMENT MATHIEU--DRIF
2025-02-21 8:07 ` [PATCH v3 19/19] intel_iommu: Add support for ATS CLEMENT MATHIEU--DRIF
2025-02-21 10:57 ` Michael S. Tsirkin [this message]
2025-02-21 12:33 ` [PATCH v3 00/19] intel_iommu: Add ATS support CLEMENT MATHIEU--DRIF
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