From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liwei1518@gmail.com,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
ajones@ventanamicro.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v2 0/3] target/riscv/kvm: reset time changes
Date: Fri, 21 Feb 2025 09:26:20 -0300 [thread overview]
Message-ID: <20250221122623.495188-1-dbarboza@ventanamicro.com> (raw)
Hi,
In this version the following changes were made, based on feedback from
Drew in v1:
- patch 2: reworked. Instead of using a different existing 'env' field
to get/put the 'sie' CSR, we're adding a new helper that contains all
reset vals for the KVM CSRs we support
- patch 3: reworked. Add two KVM CSRs from the KVM UAPI that we're not
using.
Link to v1: https://lore.kernel.org/qemu-riscv/20250220161313.127376-1-dbarboza@ventanamicro.com/
Patches based on alistair/riscv-to-apply.next.
Daniel Henrique Barboza (3):
target/riscv/cpu: ignore TCG init for KVM CPUs in reset_hold
target/riscv/kvm: add kvm_riscv_reset_regs_csr()
target/riscv/kvm: add missing KVM CSRs
target/riscv/cpu.c | 9 +++++----
target/riscv/kvm/kvm-cpu.c | 32 +++++++++++++++++++++-----------
2 files changed, 26 insertions(+), 15 deletions(-)
--
2.48.1
next reply other threads:[~2025-02-21 12:30 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-21 12:26 Daniel Henrique Barboza [this message]
2025-02-21 12:26 ` [PATCH v2 1/3] target/riscv/cpu: ignore TCG init for KVM CPUs in reset_hold Daniel Henrique Barboza
2025-02-21 12:26 ` [PATCH v2 2/3] target/riscv/kvm: add kvm_riscv_reset_regs_csr() Daniel Henrique Barboza
2025-02-21 12:44 ` Andrew Jones
2025-02-21 12:26 ` [PATCH v2 3/3] target/riscv/kvm: add missing KVM CSRs Daniel Henrique Barboza
2025-02-21 12:45 ` Andrew Jones
2025-02-28 11:10 ` [PATCH v2 0/3] target/riscv/kvm: reset time changes Daniel Henrique Barboza
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