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[142.68.128.5]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6e87b086e18sm21713286d6.44.2025.02.26.05.01.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Feb 2025 05:01:45 -0800 (PST) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1tnH2m-000000007Hf-3lRD; Wed, 26 Feb 2025 09:01:44 -0400 Date: Wed, 26 Feb 2025 09:01:44 -0400 From: Jason Gunthorpe To: "Tian, Kevin" Cc: Vasant Hegde , Robin Murphy , "Liu, Yi L" , "iommu@lists.linux.dev" , "joro@8bytes.org" , "will@kernel.org" , "suravee.suthikulpanit@amd.com" Subject: Re: [PATCH] iommu/amd: Add Secure ATS support Message-ID: <20250226130144.GE5011@ziepe.ca> References: <20250225105829.52223-1-vasant.hegde@amd.com> <20250225145518.GJ545008@ziepe.ca> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, Feb 26, 2025 at 07:10:20AM +0000, Tian, Kevin wrote: > > From: Vasant Hegde > > Sent: Wednesday, February 26, 2025 12:47 PM > > > > > > > > 3) TA is an IOVA and the IOMMU runs it through the full translation > > > to validate it. ATS is just used to signal non-present > > > > Yes. AMD does this when Host page table is configured. > > Here 'signal non-present' implies to support PRI. > > But... > > > We need to consider various scenarios. For AMD: > > - Currently on baremetal, we cannot enable SVA and Secure ATS > > ... here it says SVA/SATS are incompatible. Any more background? Yeah, +1. I don't know of use cases for #2/#3 without PRI. Why do you want it? Jason