Re: [PATCH v4 1/7] dt-bindings: usb: Introduce qcom,snps-dwc3

[Rob Herring <robh@kernel.org>]

On Wed, Feb 26, 2025 at 04:17:48PM -0800, Bjorn Andersson wrote:
> The Qualcomm USB glue is not separate of the Synopsys DWC3 core and
> several of the snps,dwc3 properties (such as clocks and reset) conflicts
> in expectation with the Qualcomm integration.
> 
> Using the newly split out Synopsys DWC3 core properties, describe the
> Qualcomm USB block in a single block. The new binding is a copy of
> qcom,dwc3 with the needed modifications.
> 
> It would have been convenient to retain the two structures with the same
> compatibles, but as there exist no way to select a binding based on the
> absence of a subnode/patternProperty, a new generic compatible is
> introduced to describe this binding.
> 
> To avoid redefining all the platform-specific compatibles, "select" is
> used to tell the DeviceTree validator which binding to use solely on the
> generic compatible. (Otherwise if the specific compatible matches during
> validation, the generic one must match as well)
> 
> Mark qcom,dwc3 deprecated, to favor expressing future platforms using
> the new combined binding.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> ---
>  .../devicetree/bindings/usb/qcom,dwc3.yaml         |  13 +-
>  .../devicetree/bindings/usb/qcom,snps-dwc3.yaml    | 619 +++++++++++++++++++++
>  2 files changed, 631 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> index a2b3cf625e5b..6d818e6dddbc 100644
> --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> @@ -4,11 +4,22 @@
>  $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
>  
> -title: Qualcomm SuperSpeed DWC3 USB SoC controller
> +title: Legacy Qualcomm SuperSpeed DWC3 USB SoC controller
>  
>  maintainers:
>    - Wesley Cheng <quic_wcheng@quicinc.com>
>  
> +# Use the combined qcom,snps-dwc3 instead
> +deprecated: true
> +
> +select:
> +  properties:
> +    compatible:
> +      contains:
> +        const: qcom,dwc3
> +  required:
> +    - compatible
> +
>  properties:
>    compatible:
>      items:
> diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
> new file mode 100644
> index 000000000000..37af52e01803
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
> @@ -0,0 +1,619 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/qcom,snps-dwc3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SuperSpeed DWC3 USB SoC controller
> +
> +maintainers:
> +  - Wesley Cheng <quic_wcheng@quicinc.com>
> +
> +description:
> +  Describes the Qualcomm USB block, based on Synopsys DWC3.
> +
> +select:
> +  properties:
> +    compatible:
> +      contains:
> +        const: qcom,snps-dwc3
> +  required:
> +    - compatible
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - qcom,ipq4019-dwc3
> +          - qcom,ipq5018-dwc3
> +          - qcom,ipq5332-dwc3
> +          - qcom,ipq5424-dwc3
> +          - qcom,ipq6018-dwc3
> +          - qcom,ipq8064-dwc3
> +          - qcom,ipq8074-dwc3
> +          - qcom,ipq9574-dwc3
> +          - qcom,msm8953-dwc3
> +          - qcom,msm8994-dwc3
> +          - qcom,msm8996-dwc3
> +          - qcom,msm8998-dwc3
> +          - qcom,qcm2290-dwc3
> +          - qcom,qcs404-dwc3
> +          - qcom,qcs615-dwc3
> +          - qcom,qcs8300-dwc3
> +          - qcom,qdu1000-dwc3
> +          - qcom,sa8775p-dwc3
> +          - qcom,sar2130p-dwc3
> +          - qcom,sc7180-dwc3
> +          - qcom,sc7280-dwc3
> +          - qcom,sc8180x-dwc3
> +          - qcom,sc8180x-dwc3-mp
> +          - qcom,sc8280xp-dwc3
> +          - qcom,sc8280xp-dwc3-mp
> +          - qcom,sdm660-dwc3
> +          - qcom,sdm670-dwc3
> +          - qcom,sdm845-dwc3
> +          - qcom,sdx55-dwc3
> +          - qcom,sdx65-dwc3
> +          - qcom,sdx75-dwc3
> +          - qcom,sm4250-dwc3
> +          - qcom,sm6115-dwc3
> +          - qcom,sm6125-dwc3
> +          - qcom,sm6350-dwc3
> +          - qcom,sm6375-dwc3
> +          - qcom,sm8150-dwc3
> +          - qcom,sm8250-dwc3
> +          - qcom,sm8350-dwc3
> +          - qcom,sm8450-dwc3
> +          - qcom,sm8550-dwc3
> +          - qcom,sm8650-dwc3
> +          - qcom,x1e80100-dwc3
> +      - const: qcom,snps-dwc3
> +
> +  reg:
> +    description: Offset and length of register set for QSCRATCH wrapper

I think you want to drop this. Or do you need 2 regions? The wrapper 
regs and the DWC3 regs? Probably worth describing separately even if 
they are adjacent currently.

> +    maxItems: 1
> +
> +  power-domains:
> +    description: specifies a phandle to PM domain provider node

Drop the description.

Otherwise, looks good.

Rob