[chunkuang-hu:mediatek-drm-next 18/18] drivers/gpu/drm/mediatek/mtk_dpi.c:662:52: error: 'DPI_OUTPUT_1T1P_EN' undeclared

[kernel test robot <lkp@intel.com>]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git mediatek-drm-next
head:   3b746eb11a87018ef92a292bba63921edb4e85fd
commit: 3b746eb11a87018ef92a292bba63921edb4e85fd [18/18] drm/mediatek: mtk_dpi: Support AFIFO 1T1P output and conversion
config: arm-randconfig-001-20250302 (https://download.01.org/0day-ci/archive/20250302/202503022243.w1kEmvNM-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250302/202503022243.w1kEmvNM-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202503022243.w1kEmvNM-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/gpu/drm/mediatek/mtk_dpi.c: In function 'mtk_dpi_set_display_mode':
>> drivers/gpu/drm/mediatek/mtk_dpi.c:662:52: error: 'DPI_OUTPUT_1T1P_EN' undeclared (first use in this function)
     662 |                         mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN, DPI_OUTPUT_1T1P_EN);
         |                                                    ^~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/mediatek/mtk_dpi.c:662:52: note: each undeclared identifier is reported only once for each function it appears in


vim +/DPI_OUTPUT_1T1P_EN +662 drivers/gpu/drm/mediatek/mtk_dpi.c

   581	
   582	static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
   583					    struct drm_display_mode *mode)
   584	{
   585		struct mtk_dpi_polarities dpi_pol;
   586		struct mtk_dpi_sync_param hsync;
   587		struct mtk_dpi_sync_param vsync_lodd = { 0 };
   588		struct mtk_dpi_sync_param vsync_leven = { 0 };
   589		struct mtk_dpi_sync_param vsync_rodd = { 0 };
   590		struct mtk_dpi_sync_param vsync_reven = { 0 };
   591		struct videomode vm = { 0 };
   592	
   593		drm_display_mode_to_videomode(mode, &vm);
   594	
   595		if (!dpi->conf->clocked_by_hdmi)
   596			mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock);
   597	
   598		dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
   599		dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
   600		dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ?
   601				    MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
   602		dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ?
   603				    MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
   604	
   605		/*
   606		 * Depending on the IP version, we may output a different amount of
   607		 * pixels for each iteration: divide the clock by this number and
   608		 * adjust the display porches accordingly.
   609		 */
   610		hsync.sync_width = vm.hsync_len / dpi->conf->pixels_per_iter;
   611		hsync.back_porch = vm.hback_porch / dpi->conf->pixels_per_iter;
   612		hsync.front_porch = vm.hfront_porch / dpi->conf->pixels_per_iter;
   613	
   614		hsync.shift_half_line = false;
   615		vsync_lodd.sync_width = vm.vsync_len;
   616		vsync_lodd.back_porch = vm.vback_porch;
   617		vsync_lodd.front_porch = vm.vfront_porch;
   618		vsync_lodd.shift_half_line = false;
   619	
   620		if (vm.flags & DISPLAY_FLAGS_INTERLACED &&
   621		    mode->flags & DRM_MODE_FLAG_3D_MASK) {
   622			vsync_leven = vsync_lodd;
   623			vsync_rodd = vsync_lodd;
   624			vsync_reven = vsync_lodd;
   625			vsync_leven.shift_half_line = true;
   626			vsync_reven.shift_half_line = true;
   627		} else if (vm.flags & DISPLAY_FLAGS_INTERLACED &&
   628			   !(mode->flags & DRM_MODE_FLAG_3D_MASK)) {
   629			vsync_leven = vsync_lodd;
   630			vsync_leven.shift_half_line = true;
   631		} else if (!(vm.flags & DISPLAY_FLAGS_INTERLACED) &&
   632			   mode->flags & DRM_MODE_FLAG_3D_MASK) {
   633			vsync_rodd = vsync_lodd;
   634		}
   635		mtk_dpi_sw_reset(dpi, true);
   636		mtk_dpi_config_pol(dpi, &dpi_pol);
   637	
   638		mtk_dpi_config_hsync(dpi, &hsync);
   639		mtk_dpi_config_vsync_lodd(dpi, &vsync_lodd);
   640		mtk_dpi_config_vsync_rodd(dpi, &vsync_rodd);
   641		mtk_dpi_config_vsync_leven(dpi, &vsync_leven);
   642		mtk_dpi_config_vsync_reven(dpi, &vsync_reven);
   643	
   644		mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK));
   645		mtk_dpi_config_interface(dpi, !!(vm.flags &
   646						 DISPLAY_FLAGS_INTERLACED));
   647		if (vm.flags & DISPLAY_FLAGS_INTERLACED)
   648			mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive >> 1);
   649		else
   650			mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive);
   651	
   652		mtk_dpi_config_channel_limit(dpi);
   653		mtk_dpi_config_bit_num(dpi, dpi->bit_num);
   654		mtk_dpi_config_channel_swap(dpi, dpi->channel_swap);
   655		mtk_dpi_config_color_format(dpi, dpi->color_format);
   656		if (dpi->conf->support_direct_pin) {
   657			mtk_dpi_config_yc_map(dpi, dpi->yc_map);
   658			mtk_dpi_config_2n_h_fre(dpi);
   659	
   660			/* DPI can connect to either an external bridge or the internal HDMI encoder */
   661			if (dpi->conf->output_1pixel)
 > 662				mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN, DPI_OUTPUT_1T1P_EN);
   663			else
   664				mtk_dpi_dual_edge(dpi);
   665	
   666			mtk_dpi_config_disable_edge(dpi);
   667		}
   668		if (dpi->conf->input_2p_en_bit) {
   669			mtk_dpi_mask(dpi, DPI_CON, dpi->conf->input_2p_en_bit,
   670				     dpi->conf->input_2p_en_bit);
   671		}
   672		mtk_dpi_sw_reset(dpi, false);
   673	
   674		return 0;
   675	}
   676	

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