From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>
Subject: [PATCH v4 1/6] hw/misc/aspeed_scu: Skipping dram_init in u-boot
Date: Mon, 3 Mar 2025 15:35:41 +0800 [thread overview]
Message-ID: <20250303073547.1145080-2-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250303073547.1145080-1-jamin_lin@aspeedtech.com>
Setting BIT6 in VGA0 SCRATCH register will indicate that the ddr traning
is done, therefore skipping the u-boot-spl dram_init() process.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index bac1441b06..50f74fbabd 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -157,6 +157,7 @@
#define AST2700_SCU_FREQ_CNTR TO_REG(0x3b0)
#define AST2700_SCU_CPU_SCRATCH_0 TO_REG(0x780)
#define AST2700_SCU_CPU_SCRATCH_1 TO_REG(0x784)
+#define AST2700_SCU_VGA_SCRATCH_0 TO_REG(0x900)
#define AST2700_SCUIO_CLK_STOP_CTL_1 TO_REG(0x240)
#define AST2700_SCUIO_CLK_STOP_CLR_1 TO_REG(0x244)
@@ -930,6 +931,7 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_SCU_FREQ_CNTR] = 0x000375eb,
[AST2700_SCU_CPU_SCRATCH_0] = 0x00000000,
[AST2700_SCU_CPU_SCRATCH_1] = 0x00000004,
+ [AST2700_SCU_VGA_SCRATCH_0] = 0x00000040,
};
static void aspeed_ast2700_scu_reset(DeviceState *dev)
--
2.34.1
next prev parent reply other threads:[~2025-03-03 7:37 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-03 7:35 [PATCH v4 0/6] Fix hw-strap for AST2700 Jamin Lin via
2025-03-03 7:35 ` Jamin Lin via
2025-03-03 7:35 ` Jamin Lin via [this message]
2025-03-03 12:27 ` [PATCH v4 1/6] hw/misc/aspeed_scu: Skipping dram_init in u-boot Cédric Le Goater
2025-03-03 7:35 ` [PATCH v4 2/6] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2700 Jamin Lin via
2025-03-03 7:35 ` Jamin Lin via
2025-03-03 13:25 ` Cédric Le Goater
2025-03-04 2:11 ` Jamin Lin
2025-03-04 6:26 ` Cédric Le Goater
2025-03-03 7:35 ` [PATCH v4 3/6] hw/arm/aspeed Update HW Strap Default Values " Jamin Lin via
2025-03-03 7:35 ` Jamin Lin via
2025-03-03 12:30 ` Cédric Le Goater
2025-03-03 7:35 ` [PATCH v4 4/6] hw/misc/aspeed_scu: Fix the hw-strap1 cannot be set in the SOC layer " Jamin Lin via
2025-03-03 7:35 ` Jamin Lin via
2025-03-03 13:31 ` Cédric Le Goater
2025-03-03 7:35 ` [PATCH v4 5/6] hw/arm/aspeed_ast27x0.c Separate HW Strap Registers for SCU and SCUIO Jamin Lin via
2025-03-03 7:35 ` Jamin Lin via
2025-03-03 13:30 ` Cédric Le Goater
2025-03-04 1:38 ` Jamin Lin
2025-03-03 7:35 ` [PATCH v4 6/6] hw/arm/aspeed_ast27x0.c Fix boot issue for AST2700 Jamin Lin via
2025-03-03 7:35 ` Jamin Lin via
2025-03-03 12:32 ` Cédric Le Goater
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