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[209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-474f09fbec6si9318651cf.168.2025.03.03.01.56.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Mar 2025 01:56:06 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nongnu.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tp2WF-0007uK-25; Mon, 03 Mar 2025 04:55:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tp2WA-0007tX-14; Mon, 03 Mar 2025 04:55:25 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tp2W8-0001gH-91; Mon, 03 Mar 2025 04:55:21 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 3 Mar 2025 17:55:01 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 3 Mar 2025 17:55:01 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v4 09/23] hw/intc/aspeed: Rename num_ints to num_inpins for clarity Date: Mon, 3 Mar 2025 17:54:37 +0800 Message-ID: <20250303095457.2337631-10-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250303095457.2337631-1-jamin_lin@aspeedtech.com> References: <20250303095457.2337631-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: /QhKEzEAioRo To support AST2700 A1, some registers of the INTC(CPU Die) support one input pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC controller code for better clarity and consistency in naming conventions. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- include/hw/intc/aspeed_intc.h | 11 ++++++----- hw/arm/aspeed_ast27x0.c | 2 +- hw/intc/aspeed_intc.c | 31 +++++++++++++++++-------------- 3 files changed, 24 insertions(+), 20 deletions(-) diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h index c1fe2dd15a..4a0512c688 100644 --- a/include/hw/intc/aspeed_intc.h +++ b/include/hw/intc/aspeed_intc.h @@ -18,6 +18,7 @@ OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC) #define ASPEED_INTC_NR_REGS (0x808 >> 2) #define ASPEED_INTC_NR_INTS 9 +#define ASPEED_INTC_MAX_INPINS 9 struct AspeedINTCState { /*< private >*/ @@ -28,19 +29,19 @@ struct AspeedINTCState { MemoryRegion iomem_container; uint32_t regs[ASPEED_INTC_NR_REGS]; - OrIRQState orgates[ASPEED_INTC_NR_INTS]; + OrIRQState orgates[ASPEED_INTC_MAX_INPINS]; qemu_irq output_pins[ASPEED_INTC_NR_INTS]; - uint32_t enable[ASPEED_INTC_NR_INTS]; - uint32_t mask[ASPEED_INTC_NR_INTS]; - uint32_t pending[ASPEED_INTC_NR_INTS]; + uint32_t enable[ASPEED_INTC_MAX_INPINS]; + uint32_t mask[ASPEED_INTC_MAX_INPINS]; + uint32_t pending[ASPEED_INTC_MAX_INPINS]; }; struct AspeedINTCClass { SysBusDeviceClass parent_class; uint32_t num_lines; - uint32_t num_ints; + uint32_t num_inpins; uint64_t mem_size; uint64_t reg_size; uint64_t reg_offset; diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index b44d23b5ae..9aea06fb76 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -531,7 +531,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) sc->memmap[ASPEED_DEV_INTC]); /* GICINT orgates -> INTC -> GIC */ - for (i = 0; i < ic->num_ints; i++) { + for (i = 0; i < ic->num_inpins; i++) { qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0, qdev_get_gpio_in(DEVICE(&a->intc), i)); sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i, diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 90658ffb59..f9f30c957e 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -47,8 +47,9 @@ static void aspeed_intc_update(AspeedINTCState *s, int irq, int level) AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); const char *name = object_get_typename(OBJECT(s)); - if (irq >= aic->num_ints) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n", + if (irq >= aic->num_inpins) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid input pin index: %d\n", __func__, irq); return; } @@ -60,7 +61,7 @@ static void aspeed_intc_update(AspeedINTCState *s, int irq, int level) /* * The address of GICINT128 to GICINT136 are from 0x1000 to 0x1804. * Utilize "address & 0x0f00" to get the irq and irq output pin index - * The value of irq should be 0 to num_ints. + * The value of irq should be 0 to num_inpins. * The irq 0 indicates GICINT128, irq 1 indicates GICINT129 and so on. */ static void aspeed_intc_set_irq(void *opaque, int irq, int level) @@ -73,8 +74,8 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level) uint32_t enable; int i; - if (irq >= aic->num_ints) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n", + if (irq >= aic->num_inpins) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid input pin index: %d\n", __func__, irq); return; } @@ -134,8 +135,9 @@ static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset, irq = (offset & 0x0f00) >> 8; - if (irq >= aic->num_ints) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n", + if (irq >= aic->num_inpins) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid input pin index: %d\n", __func__, irq); return; } @@ -190,8 +192,9 @@ static void aspeed_intc_status_handler(AspeedINTCState *s, hwaddr offset, irq = (offset & 0x0f00) >> 8; - if (irq >= aic->num_ints) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n", + if (irq >= aic->num_inpins) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid input pin index: %d\n", __func__, irq); return; } @@ -315,8 +318,8 @@ static void aspeed_intc_instance_init(Object *obj) AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); int i; - assert(aic->num_ints <= ASPEED_INTC_NR_INTS); - for (i = 0; i < aic->num_ints; i++) { + assert(aic->num_inpins <= ASPEED_INTC_MAX_INPINS); + for (i = 0; i < aic->num_inpins; i++) { object_initialize_child(obj, "intc-orgates[*]", &s->orgates[i], TYPE_OR_IRQ); object_property_set_int(OBJECT(&s->orgates[i]), "num-lines", @@ -352,9 +355,9 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(&s->iomem_container, aic->reg_offset, &s->iomem); - qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_ints); + qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_inpins); - for (i = 0; i < aic->num_ints; i++) { + for (i = 0; i < aic->num_inpins; i++) { if (!qdev_realize(DEVICE(&s->orgates[i]), NULL, errp)) { return; } @@ -392,7 +395,7 @@ static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data) dc->desc = "ASPEED 2700 INTC Controller"; aic->num_lines = 32; - aic->num_ints = 9; + aic->num_inpins = 9; aic->mem_size = 0x4000; aic->reg_size = 0x808; aic->reg_offset = 0x1000; -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D650EC282C5 for ; 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Mon, 3 Mar 2025 17:55:01 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v4 09/23] hw/intc/aspeed: Rename num_ints to num_inpins for clarity Date: Mon, 3 Mar 2025 17:54:37 +0800 Message-ID: <20250303095457.2337631-10-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250303095457.2337631-1-jamin_lin@aspeedtech.com> References: <20250303095457.2337631-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org To support AST2700 A1, some registers of the INTC(CPU Die) support one input pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC controller code for better clarity and consistency in naming conventions. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- include/hw/intc/aspeed_intc.h | 11 ++++++----- hw/arm/aspeed_ast27x0.c | 2 +- hw/intc/aspeed_intc.c | 31 +++++++++++++++++-------------- 3 files changed, 24 insertions(+), 20 deletions(-) diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h index c1fe2dd15a..4a0512c688 100644 --- a/include/hw/intc/aspeed_intc.h +++ b/include/hw/intc/aspeed_intc.h @@ -18,6 +18,7 @@ OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC) #define ASPEED_INTC_NR_REGS (0x808 >> 2) #define ASPEED_INTC_NR_INTS 9 +#define ASPEED_INTC_MAX_INPINS 9 struct AspeedINTCState { /*< private >*/ @@ -28,19 +29,19 @@ struct AspeedINTCState { MemoryRegion iomem_container; uint32_t regs[ASPEED_INTC_NR_REGS]; - OrIRQState orgates[ASPEED_INTC_NR_INTS]; + OrIRQState orgates[ASPEED_INTC_MAX_INPINS]; qemu_irq output_pins[ASPEED_INTC_NR_INTS]; - uint32_t enable[ASPEED_INTC_NR_INTS]; - uint32_t mask[ASPEED_INTC_NR_INTS]; - uint32_t pending[ASPEED_INTC_NR_INTS]; + uint32_t enable[ASPEED_INTC_MAX_INPINS]; + uint32_t mask[ASPEED_INTC_MAX_INPINS]; + uint32_t pending[ASPEED_INTC_MAX_INPINS]; }; struct AspeedINTCClass { SysBusDeviceClass parent_class; uint32_t num_lines; - uint32_t num_ints; + uint32_t num_inpins; uint64_t mem_size; uint64_t reg_size; uint64_t reg_offset; diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index b44d23b5ae..9aea06fb76 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -531,7 +531,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) sc->memmap[ASPEED_DEV_INTC]); /* GICINT orgates -> INTC -> GIC */ - for (i = 0; i < ic->num_ints; i++) { + for (i = 0; i < ic->num_inpins; i++) { qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0, qdev_get_gpio_in(DEVICE(&a->intc), i)); sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i, diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 90658ffb59..f9f30c957e 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -47,8 +47,9 @@ static void aspeed_intc_update(AspeedINTCState *s, int irq, int level) AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); const char *name = object_get_typename(OBJECT(s)); - if (irq >= aic->num_ints) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n", + if (irq >= aic->num_inpins) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid input pin index: %d\n", __func__, irq); return; } @@ -60,7 +61,7 @@ static void aspeed_intc_update(AspeedINTCState *s, int irq, int level) /* * The address of GICINT128 to GICINT136 are from 0x1000 to 0x1804. * Utilize "address & 0x0f00" to get the irq and irq output pin index - * The value of irq should be 0 to num_ints. + * The value of irq should be 0 to num_inpins. * The irq 0 indicates GICINT128, irq 1 indicates GICINT129 and so on. */ static void aspeed_intc_set_irq(void *opaque, int irq, int level) @@ -73,8 +74,8 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level) uint32_t enable; int i; - if (irq >= aic->num_ints) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n", + if (irq >= aic->num_inpins) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid input pin index: %d\n", __func__, irq); return; } @@ -134,8 +135,9 @@ static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset, irq = (offset & 0x0f00) >> 8; - if (irq >= aic->num_ints) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n", + if (irq >= aic->num_inpins) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid input pin index: %d\n", __func__, irq); return; } @@ -190,8 +192,9 @@ static void aspeed_intc_status_handler(AspeedINTCState *s, hwaddr offset, irq = (offset & 0x0f00) >> 8; - if (irq >= aic->num_ints) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n", + if (irq >= aic->num_inpins) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid input pin index: %d\n", __func__, irq); return; } @@ -315,8 +318,8 @@ static void aspeed_intc_instance_init(Object *obj) AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); int i; - assert(aic->num_ints <= ASPEED_INTC_NR_INTS); - for (i = 0; i < aic->num_ints; i++) { + assert(aic->num_inpins <= ASPEED_INTC_MAX_INPINS); + for (i = 0; i < aic->num_inpins; i++) { object_initialize_child(obj, "intc-orgates[*]", &s->orgates[i], TYPE_OR_IRQ); object_property_set_int(OBJECT(&s->orgates[i]), "num-lines", @@ -352,9 +355,9 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(&s->iomem_container, aic->reg_offset, &s->iomem); - qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_ints); + qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_inpins); - for (i = 0; i < aic->num_ints; i++) { + for (i = 0; i < aic->num_inpins; i++) { if (!qdev_realize(DEVICE(&s->orgates[i]), NULL, errp)) { return; } @@ -392,7 +395,7 @@ static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data) dc->desc = "ASPEED 2700 INTC Controller"; aic->num_lines = 32; - aic->num_ints = 9; + aic->num_inpins = 9; aic->mem_size = 0x4000; aic->reg_size = 0x808; aic->reg_offset = 0x1000; -- 2.34.1