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[142.68.128.5]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6e8976ccbefsm66733706d6.85.2025.03.04.06.20.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 06:20:31 -0800 (PST) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1tpT8I-0000000176Z-3IJw; Tue, 04 Mar 2025 10:20:30 -0400 Date: Tue, 4 Mar 2025 10:20:30 -0400 From: Jason Gunthorpe To: Yi Liu Cc: Vasant Hegde , "Tian, Kevin" , Robin Murphy , "iommu@lists.linux.dev" , "joro@8bytes.org" , "will@kernel.org" , "suravee.suthikulpanit@amd.com" Subject: Re: [PATCH] iommu/amd: Add Secure ATS support Message-ID: <20250304142030.GA5011@ziepe.ca> References: <4fba254e-ca47-4e7b-baf3-0228d9605c2b@amd.com> <942a1a66-5c18-43e2-886e-df38cb3e7258@intel.com> <54db17d7-b150-4579-a33d-f1b5cc8943bc@amd.com> <6eb0ec90-5859-4605-8a2e-657f6f711d61@intel.com> <825ddadd-6770-46b5-936e-f17988534984@amd.com> <13e1e1d8-5870-44ea-a800-e5b25bafd344@intel.com> <20250303183801.GW5011@ziepe.ca> <2c9ef073-fee5-43c6-8932-a8cae677970e@intel.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2c9ef073-fee5-43c6-8932-a8cae677970e@intel.com> On Tue, Mar 04, 2025 at 02:50:19PM +0800, Yi Liu wrote: > > ARM enables ATS when a PAGING translation is set on the RID or any > > PASID is used. Otherwise it is off, eg for RID = IDENTITY > > > > This seems like a reasonable thing to do to me.. > > will it affect Baolu's above refactoring [1]? :( I think no, but when we get some conclusion how ATS should work I'd expect all IOMMU drivers to align > > never > > always > > paging-only > > this can be considered policy to the existing ATS. curious, why paging > domain is special here? Using ATS with an IDENTITY translation is not a performance win, so you'd probably want to turn it off in that case. Jason