From: Cornelia Huck <cohuck@redhat.com>
To: eric.auger.pro@gmail.com, eric.auger@redhat.com,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
kvmarm@lists.linux.dev, peter.maydell@linaro.org,
richard.henderson@linaro.org, alex.bennee@linaro.org,
maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com,
shameerali.kolothum.thodi@huawei.com, armbru@redhat.com,
berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com,
agraf@csgraf.de
Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org,
pbonzini@redhat.com, Cornelia Huck <cohuck@redhat.com>
Subject: [PATCH v2 14/14] arm/cpu: Add generated files
Date: Wed, 5 Mar 2025 17:38:19 +0100 [thread overview]
Message-ID: <20250305163819.2477553-15-cohuck@redhat.com> (raw)
In-Reply-To: <20250305163819.2477553-1-cohuck@redhat.com>
And switch to using the generated definitions.
Generated against Linux 6.14-rc1.
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-sysregs.h | 116 +-----------------------
target/arm/cpu-sysregs.h.inc | 167 +++++++++++++++++++++++++++++++++++
2 files changed, 169 insertions(+), 114 deletions(-)
create mode 100644 target/arm/cpu-sysregs.h.inc
diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
index 54a4fadbf0c1..6074516c6d2c 100644
--- a/target/arm/cpu-sysregs.h
+++ b/target/arm/cpu-sysregs.h
@@ -13,120 +13,8 @@
((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
-typedef enum ARMIDRegisterIdx {
- ID_AA64PFR0_EL1_IDX,
- ID_AA64PFR1_EL1_IDX,
- ID_AA64SMFR0_EL1_IDX,
- ID_AA64DFR0_EL1_IDX,
- ID_AA64DFR1_EL1_IDX,
- ID_AA64ISAR0_EL1_IDX,
- ID_AA64ISAR1_EL1_IDX,
- ID_AA64ISAR2_EL1_IDX,
- ID_AA64MMFR0_EL1_IDX,
- ID_AA64MMFR1_EL1_IDX,
- ID_AA64MMFR2_EL1_IDX,
- ID_AA64MMFR3_EL1_IDX,
- ID_PFR0_EL1_IDX,
- ID_PFR1_EL1_IDX,
- ID_DFR0_EL1_IDX,
- ID_MMFR0_EL1_IDX,
- ID_MMFR1_EL1_IDX,
- ID_MMFR2_EL1_IDX,
- ID_MMFR3_EL1_IDX,
- ID_ISAR0_EL1_IDX,
- ID_ISAR1_EL1_IDX,
- ID_ISAR2_EL1_IDX,
- ID_ISAR3_EL1_IDX,
- ID_ISAR4_EL1_IDX,
- ID_ISAR5_EL1_IDX,
- ID_MMFR4_EL1_IDX,
- ID_ISAR6_EL1_IDX,
- MVFR0_EL1_IDX,
- MVFR1_EL1_IDX,
- MVFR2_EL1_IDX,
- ID_PFR2_EL1_IDX,
- ID_DFR1_EL1_IDX,
- ID_MMFR5_EL1_IDX,
- ID_AA64ZFR0_EL1_IDX,
- CTR_EL0_IDX,
- NUM_ID_IDX,
-} ARMIDRegisterIdx;
-
-typedef enum ARMSysRegs {
- SYS_ID_AA64PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 0),
- SYS_ID_AA64PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 1),
- SYS_ID_AA64SMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 5),
- SYS_ID_AA64DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 0),
- SYS_ID_AA64DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 1),
- SYS_ID_AA64ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 0),
- SYS_ID_AA64ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 1),
- SYS_ID_AA64ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 2),
- SYS_ID_AA64MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 0),
- SYS_ID_AA64MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 1),
- SYS_ID_AA64MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 2),
- SYS_ID_AA64MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 3),
- SYS_ID_PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 0),
- SYS_ID_PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 1),
- SYS_ID_DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 2),
- SYS_ID_MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 4),
- SYS_ID_MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 5),
- SYS_ID_MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 6),
- SYS_ID_MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 7),
- SYS_ID_ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 0),
- SYS_ID_ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 1),
- SYS_ID_ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 2),
- SYS_ID_ISAR3_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 3),
- SYS_ID_ISAR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 4),
- SYS_ID_ISAR5_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 5),
- SYS_ID_MMFR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 6),
- SYS_ID_ISAR6_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 7),
- SYS_MVFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 0),
- SYS_MVFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 1),
- SYS_MVFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 2),
- SYS_ID_PFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 4),
- SYS_ID_DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 5),
- SYS_ID_MMFR5_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 6),
- SYS_ID_AA64ZFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 4),
- SYS_CTR_EL0 = ENCODE_ID_REG(3, 3, 0, 0, 1),
-} ARMSysRegs;
-
-static const uint32_t id_register_sysreg[NUM_ID_IDX] = {
- [ID_AA64PFR0_EL1_IDX] = SYS_ID_AA64PFR0_EL1,
- [ID_AA64PFR1_EL1_IDX] = SYS_ID_AA64PFR1_EL1,
- [ID_AA64SMFR0_EL1_IDX] = SYS_ID_AA64SMFR0_EL1,
- [ID_AA64DFR0_EL1_IDX] = SYS_ID_AA64DFR0_EL1,
- [ID_AA64DFR1_EL1_IDX] = SYS_ID_AA64DFR1_EL1,
- [ID_AA64ISAR0_EL1_IDX] = SYS_ID_AA64ISAR0_EL1,
- [ID_AA64ISAR1_EL1_IDX] = SYS_ID_AA64ISAR1_EL1,
- [ID_AA64ISAR2_EL1_IDX] = SYS_ID_AA64ISAR2_EL1,
- [ID_AA64MMFR0_EL1_IDX] = SYS_ID_AA64MMFR0_EL1,
- [ID_AA64MMFR1_EL1_IDX] = SYS_ID_AA64MMFR1_EL1,
- [ID_AA64MMFR2_EL1_IDX] = SYS_ID_AA64MMFR2_EL1,
- [ID_AA64MMFR3_EL1_IDX] = SYS_ID_AA64MMFR3_EL1,
- [ID_PFR0_EL1_IDX] = SYS_ID_PFR0_EL1,
- [ID_PFR1_EL1_IDX] = SYS_ID_PFR1_EL1,
- [ID_DFR0_EL1_IDX] = SYS_ID_DFR0_EL1,
- [ID_MMFR0_EL1_IDX] = SYS_ID_MMFR0_EL1,
- [ID_MMFR1_EL1_IDX] = SYS_ID_MMFR1_EL1,
- [ID_MMFR2_EL1_IDX] = SYS_ID_MMFR2_EL1,
- [ID_MMFR3_EL1_IDX] = SYS_ID_MMFR3_EL1,
- [ID_ISAR0_EL1_IDX] = SYS_ID_ISAR0_EL1,
- [ID_ISAR1_EL1_IDX] = SYS_ID_ISAR1_EL1,
- [ID_ISAR2_EL1_IDX] = SYS_ID_ISAR2_EL1,
- [ID_ISAR3_EL1_IDX] = SYS_ID_ISAR3_EL1,
- [ID_ISAR4_EL1_IDX] = SYS_ID_ISAR4_EL1,
- [ID_ISAR5_EL1_IDX] = SYS_ID_ISAR5_EL1,
- [ID_MMFR4_EL1_IDX] = SYS_ID_MMFR4_EL1,
- [ID_ISAR6_EL1_IDX] = SYS_ID_ISAR6_EL1,
- [MVFR0_EL1_IDX] = SYS_MVFR0_EL1,
- [MVFR1_EL1_IDX] = SYS_MVFR1_EL1,
- [MVFR2_EL1_IDX] = SYS_MVFR2_EL1,
- [ID_PFR2_EL1_IDX] = SYS_ID_PFR2_EL1,
- [ID_DFR1_EL1_IDX] = SYS_ID_DFR1_EL1,
- [ID_MMFR5_EL1_IDX] = SYS_ID_MMFR5_EL1,
- [ID_AA64ZFR0_EL1_IDX] = SYS_ID_AA64ZFR0_EL1,
- [CTR_EL0_IDX] = SYS_CTR_EL0,
-};
+/* include generated definitions */
+#include "cpu-sysregs.h.inc"
int get_sysreg_idx(ARMSysRegs sysreg);
uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg);
diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
new file mode 100644
index 000000000000..9236c36696df
--- /dev/null
+++ b/target/arm/cpu-sysregs.h.inc
@@ -0,0 +1,167 @@
+/* GENERATED FILE -- DO NOT EDIT */
+#ifndef ARCH_ARM_CPU_SYSREGS_H_INC
+#define ARCH_ARM_CPU_SYSREGS_H_INC
+
+typedef enum ARMIDRegisterIdx {
+ ID_PFR0_EL1_IDX,
+ ID_PFR1_EL1_IDX,
+ ID_DFR0_EL1_IDX,
+ ID_AFR0_EL1_IDX,
+ ID_MMFR0_EL1_IDX,
+ ID_MMFR1_EL1_IDX,
+ ID_MMFR2_EL1_IDX,
+ ID_MMFR3_EL1_IDX,
+ ID_ISAR0_EL1_IDX,
+ ID_ISAR1_EL1_IDX,
+ ID_ISAR2_EL1_IDX,
+ ID_ISAR3_EL1_IDX,
+ ID_ISAR4_EL1_IDX,
+ ID_ISAR5_EL1_IDX,
+ ID_ISAR6_EL1_IDX,
+ ID_MMFR4_EL1_IDX,
+ MVFR0_EL1_IDX,
+ MVFR1_EL1_IDX,
+ MVFR2_EL1_IDX,
+ ID_PFR2_EL1_IDX,
+ ID_DFR1_EL1_IDX,
+ ID_MMFR5_EL1_IDX,
+ ID_AA64PFR0_EL1_IDX,
+ ID_AA64PFR1_EL1_IDX,
+ ID_AA64PFR2_EL1_IDX,
+ ID_AA64ZFR0_EL1_IDX,
+ ID_AA64SMFR0_EL1_IDX,
+ ID_AA64FPFR0_EL1_IDX,
+ ID_AA64DFR0_EL1_IDX,
+ ID_AA64DFR1_EL1_IDX,
+ ID_AA64DFR2_EL1_IDX,
+ ID_AA64AFR0_EL1_IDX,
+ ID_AA64AFR1_EL1_IDX,
+ ID_AA64ISAR0_EL1_IDX,
+ ID_AA64ISAR1_EL1_IDX,
+ ID_AA64ISAR2_EL1_IDX,
+ ID_AA64ISAR3_EL1_IDX,
+ ID_AA64MMFR0_EL1_IDX,
+ ID_AA64MMFR1_EL1_IDX,
+ ID_AA64MMFR2_EL1_IDX,
+ ID_AA64MMFR3_EL1_IDX,
+ ID_AA64MMFR4_EL1_IDX,
+ CCSIDR_EL1_IDX,
+ CLIDR_EL1_IDX,
+ CCSIDR2_EL1_IDX,
+ GMID_EL1_IDX,
+ SMIDR_EL1_IDX,
+ CSSELR_EL1_IDX,
+ CTR_EL0_IDX,
+ DCZID_EL0_IDX,
+ NUM_ID_IDX,
+} ARMIDRegisterIdx;
+
+
+typedef enum ARMSysRegs {
+ SYS_ID_PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 0),
+ SYS_ID_PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 1),
+ SYS_ID_DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 2),
+ SYS_ID_AFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 3),
+ SYS_ID_MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 4),
+ SYS_ID_MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 5),
+ SYS_ID_MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 6),
+ SYS_ID_MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 7),
+ SYS_ID_ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 0),
+ SYS_ID_ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 1),
+ SYS_ID_ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 2),
+ SYS_ID_ISAR3_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 3),
+ SYS_ID_ISAR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 4),
+ SYS_ID_ISAR5_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 5),
+ SYS_ID_ISAR6_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 7),
+ SYS_ID_MMFR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 6),
+ SYS_MVFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 0),
+ SYS_MVFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 1),
+ SYS_MVFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 2),
+ SYS_ID_PFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 4),
+ SYS_ID_DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 5),
+ SYS_ID_MMFR5_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 6),
+ SYS_ID_AA64PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 0),
+ SYS_ID_AA64PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 1),
+ SYS_ID_AA64PFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 2),
+ SYS_ID_AA64ZFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 4),
+ SYS_ID_AA64SMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 5),
+ SYS_ID_AA64FPFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 7),
+ SYS_ID_AA64DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 0),
+ SYS_ID_AA64DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 1),
+ SYS_ID_AA64DFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 2),
+ SYS_ID_AA64AFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 4),
+ SYS_ID_AA64AFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 5),
+ SYS_ID_AA64ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 0),
+ SYS_ID_AA64ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 1),
+ SYS_ID_AA64ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 2),
+ SYS_ID_AA64ISAR3_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 3),
+ SYS_ID_AA64MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 0),
+ SYS_ID_AA64MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 1),
+ SYS_ID_AA64MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 2),
+ SYS_ID_AA64MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 3),
+ SYS_ID_AA64MMFR4_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 4),
+ SYS_CCSIDR_EL1 = ENCODE_ID_REG(3, 1, 0, 0, 0),
+ SYS_CLIDR_EL1 = ENCODE_ID_REG(3, 1, 0, 0, 1),
+ SYS_CCSIDR2_EL1 = ENCODE_ID_REG(3, 1, 0, 0, 2),
+ SYS_GMID_EL1 = ENCODE_ID_REG(3, 1, 0, 0, 4),
+ SYS_SMIDR_EL1 = ENCODE_ID_REG(3, 1, 0, 0, 6),
+ SYS_CSSELR_EL1 = ENCODE_ID_REG(3, 2, 0, 0, 0),
+ SYS_CTR_EL0 = ENCODE_ID_REG(3, 3, 0, 0, 1),
+ SYS_DCZID_EL0 = ENCODE_ID_REG(3, 3, 0, 0, 7),
+} ARMSysRegs;
+
+
+static const uint32_t id_register_sysreg[NUM_ID_IDX] = {
+ [ID_PFR0_EL1_IDX] = SYS_ID_PFR0_EL1,
+ [ID_PFR1_EL1_IDX] = SYS_ID_PFR1_EL1,
+ [ID_DFR0_EL1_IDX] = SYS_ID_DFR0_EL1,
+ [ID_AFR0_EL1_IDX] = SYS_ID_AFR0_EL1,
+ [ID_MMFR0_EL1_IDX] = SYS_ID_MMFR0_EL1,
+ [ID_MMFR1_EL1_IDX] = SYS_ID_MMFR1_EL1,
+ [ID_MMFR2_EL1_IDX] = SYS_ID_MMFR2_EL1,
+ [ID_MMFR3_EL1_IDX] = SYS_ID_MMFR3_EL1,
+ [ID_ISAR0_EL1_IDX] = SYS_ID_ISAR0_EL1,
+ [ID_ISAR1_EL1_IDX] = SYS_ID_ISAR1_EL1,
+ [ID_ISAR2_EL1_IDX] = SYS_ID_ISAR2_EL1,
+ [ID_ISAR3_EL1_IDX] = SYS_ID_ISAR3_EL1,
+ [ID_ISAR4_EL1_IDX] = SYS_ID_ISAR4_EL1,
+ [ID_ISAR5_EL1_IDX] = SYS_ID_ISAR5_EL1,
+ [ID_ISAR6_EL1_IDX] = SYS_ID_ISAR6_EL1,
+ [ID_MMFR4_EL1_IDX] = SYS_ID_MMFR4_EL1,
+ [MVFR0_EL1_IDX] = SYS_MVFR0_EL1,
+ [MVFR1_EL1_IDX] = SYS_MVFR1_EL1,
+ [MVFR2_EL1_IDX] = SYS_MVFR2_EL1,
+ [ID_PFR2_EL1_IDX] = SYS_ID_PFR2_EL1,
+ [ID_DFR1_EL1_IDX] = SYS_ID_DFR1_EL1,
+ [ID_MMFR5_EL1_IDX] = SYS_ID_MMFR5_EL1,
+ [ID_AA64PFR0_EL1_IDX] = SYS_ID_AA64PFR0_EL1,
+ [ID_AA64PFR1_EL1_IDX] = SYS_ID_AA64PFR1_EL1,
+ [ID_AA64PFR2_EL1_IDX] = SYS_ID_AA64PFR2_EL1,
+ [ID_AA64ZFR0_EL1_IDX] = SYS_ID_AA64ZFR0_EL1,
+ [ID_AA64SMFR0_EL1_IDX] = SYS_ID_AA64SMFR0_EL1,
+ [ID_AA64FPFR0_EL1_IDX] = SYS_ID_AA64FPFR0_EL1,
+ [ID_AA64DFR0_EL1_IDX] = SYS_ID_AA64DFR0_EL1,
+ [ID_AA64DFR1_EL1_IDX] = SYS_ID_AA64DFR1_EL1,
+ [ID_AA64DFR2_EL1_IDX] = SYS_ID_AA64DFR2_EL1,
+ [ID_AA64AFR0_EL1_IDX] = SYS_ID_AA64AFR0_EL1,
+ [ID_AA64AFR1_EL1_IDX] = SYS_ID_AA64AFR1_EL1,
+ [ID_AA64ISAR0_EL1_IDX] = SYS_ID_AA64ISAR0_EL1,
+ [ID_AA64ISAR1_EL1_IDX] = SYS_ID_AA64ISAR1_EL1,
+ [ID_AA64ISAR2_EL1_IDX] = SYS_ID_AA64ISAR2_EL1,
+ [ID_AA64ISAR3_EL1_IDX] = SYS_ID_AA64ISAR3_EL1,
+ [ID_AA64MMFR0_EL1_IDX] = SYS_ID_AA64MMFR0_EL1,
+ [ID_AA64MMFR1_EL1_IDX] = SYS_ID_AA64MMFR1_EL1,
+ [ID_AA64MMFR2_EL1_IDX] = SYS_ID_AA64MMFR2_EL1,
+ [ID_AA64MMFR3_EL1_IDX] = SYS_ID_AA64MMFR3_EL1,
+ [ID_AA64MMFR4_EL1_IDX] = SYS_ID_AA64MMFR4_EL1,
+ [CCSIDR_EL1_IDX] = SYS_CCSIDR_EL1,
+ [CLIDR_EL1_IDX] = SYS_CLIDR_EL1,
+ [CCSIDR2_EL1_IDX] = SYS_CCSIDR2_EL1,
+ [GMID_EL1_IDX] = SYS_GMID_EL1,
+ [SMIDR_EL1_IDX] = SYS_SMIDR_EL1,
+ [CSSELR_EL1_IDX] = SYS_CSSELR_EL1,
+ [CTR_EL0_IDX] = SYS_CTR_EL0,
+ [DCZID_EL0_IDX] = SYS_DCZID_EL0,
+};
+
+#endif /* ARCH_ARM_CPU_SYSREGS_H_INC */
--
2.48.1
prev parent reply other threads:[~2025-03-05 16:42 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-05 16:38 [PATCH v2 00/14] arm: rework id register storage Cornelia Huck
2025-03-05 16:38 ` [PATCH v2 01/14] arm/cpu: Add sysreg definitions in cpu-sysregs.h Cornelia Huck
2025-03-06 1:14 ` Richard Henderson
2025-03-07 15:32 ` Cornelia Huck
2025-03-05 16:38 ` [PATCH v2 02/14] arm/kvm: add accessors for storing host features into idregs Cornelia Huck
2025-03-06 1:15 ` Richard Henderson
2025-03-07 15:35 ` Cornelia Huck
2025-03-05 16:38 ` [PATCH v2 03/14] arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays Cornelia Huck
2025-03-05 16:38 ` [PATCH v2 04/14] arm/cpu: Store aa64isar1/2 into the idregs array Cornelia Huck
2025-03-05 16:38 ` [PATCH v2 05/14] arm/cpu: Store aa64pfr0/1 " Cornelia Huck
2025-03-05 16:38 ` [PATCH v2 06/14] arm/cpu: Store aa64mmfr0-3 " Cornelia Huck
2025-03-05 16:38 ` [PATCH v2 07/14] arm/cpu: Store aa64dfr0/1 " Cornelia Huck
2025-03-05 16:38 ` [PATCH v2 08/14] arm/cpu: Store aa64smfr0 " Cornelia Huck
2025-03-05 16:38 ` [PATCH v2 09/14] arm/cpu: Store id_isar0-7 " Cornelia Huck
2025-03-05 16:38 ` [PATCH v2 10/14] arm/cpu: Store id_pfr0/1/2 " Cornelia Huck
2025-03-05 16:38 ` [PATCH v2 11/14] arm/cpu: Store id_dfr0/1 " Cornelia Huck
2025-03-05 16:38 ` [PATCH v2 12/14] arm/cpu: Store id_mmfr0-5 " Cornelia Huck
2025-03-05 16:38 ` [PATCH v2 13/14] arm/cpu: Add sysreg generation scripts Cornelia Huck
2025-03-05 16:38 ` Cornelia Huck [this message]
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