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[75.72.162.184]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6e8f715b798sm78025286d6.80.2025.03.11.17.31.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 17:31:47 -0700 (PDT) From: Adam Ford To: u-boot@lists.denx.de Cc: aford@beaconembedded.com, Adam Ford , Tom Rini , Lukasz Majewski , Sean Anderson , Stefano Babic , Fabio Estevam , "NXP i.MX U-Boot Team" , Simon Glass , Sumit Garg , Quentin Schulz , Marek Vasut , Emil Kronborg , Michael Trimarchi , Tim Harvey , Hou Zhiqiang , Peter Robinson Subject: [PATCH V2 02/10] clk: imx6q: Register UART clocks Date: Tue, 11 Mar 2025 19:30:22 -0500 Message-ID: <20250312003041.110023-3-aford173@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250312003041.110023-1-aford173@gmail.com> References: <20250312003041.110023-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean In order to use the driver model and clock system to enable UART clocks from the serial driver, it's necessary to register the UART clocks. With the helper function to check for imx6qp vs other variants, the UART can register for both scenarios. Signed-off-by: Adam Ford --- V2: Directly call of_machine_is_compatible("fsl,imx6qp") instead of using a helper function --- drivers/clk/imx/clk-imx6q.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 15ad0c9ac06..a4295614016 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -35,6 +35,7 @@ static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; static const char *const periph_sels[] = { "periph_pre", "periph_clk2", }; static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; +static const char *const uart_sels[] = { "pll3_80m", "osc", }; static const char *const ecspi_sels[] = { "pll3_60m", "osc", }; static int imx6q_clk_probe(struct udevice *dev) @@ -79,10 +80,14 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); - if (of_machine_is_compatible("fsl,imx6qp") + if (of_machine_is_compatible("fsl,imx6qp") { + clk_dm(IMX6QDL_CLK_UART_SEL, + imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, + ARRAY_SIZE(uart_sels))); clk_dm(IMX6QDL_CLK_ECSPI_SEL, imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels))); + } clk_dm(IMX6QDL_CLK_USDHC1_PODF, imx_clk_divider("usdhc1_podf", "usdhc1_sel", @@ -97,12 +102,17 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3)); - if (of_machine_is_compatible("fsl,imx6qp") + if (of_machine_is_compatible("fsl,imx6qp") { + clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF, + imx_clk_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6)); clk_dm(IMX6QDL_CLK_ECSPI_ROOT, imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6)); - else + } else { + clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF, + imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6)); clk_dm(IMX6QDL_CLK_ECSPI_ROOT, imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6)); + } clk_dm(IMX6QDL_CLK_ECSPI1, imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0)); @@ -112,6 +122,10 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4)); clk_dm(IMX6QDL_CLK_ECSPI4, imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6)); + clk_dm(IMX6QDL_CLK_UART_IPG, + imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24)); + clk_dm(IMX6QDL_CLK_UART_SERIAL, + imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26)); clk_dm(IMX6QDL_CLK_USDHC1, imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2)); clk_dm(IMX6QDL_CLK_USDHC2, -- 2.45.2