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Thu, 13 Mar 2025 06:19:33 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200::59a5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3147ead1dsm81138266b.58.2025.03.13.06.19.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 06:19:33 -0700 (PDT) Date: Thu, 13 Mar 2025 14:19:32 +0100 From: Andrew Jones To: =?utf-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= Cc: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Samuel Holland Subject: Re: [PATCH v3 08/17] riscv: misaligned: add a function to check misalign trap delegability Message-ID: <20250313-4bea400c5770a5a5d3d70b38@orel> References: <20250310151229.2365992-1-cleger@rivosinc.com> <20250310151229.2365992-9-cleger@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250310151229.2365992-9-cleger@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250313_061936_146693_F03A3A7F X-CRM114-Status: GOOD ( 19.27 ) X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+kvm-riscv=archiver.kernel.org@lists.infradead.org On Mon, Mar 10, 2025 at 04:12:15PM +0100, Cl=E9ment L=E9ger wrote: > Checking for the delegability of the misaligned access trap is needed > for the KVM FWFT extension implementation. Add a function to get the > delegability of the misaligned trap exception. > = > Signed-off-by: Cl=E9ment L=E9ger > --- > arch/riscv/include/asm/cpufeature.h | 5 +++++ > arch/riscv/kernel/traps_misaligned.c | 17 +++++++++++++++-- > 2 files changed, 20 insertions(+), 2 deletions(-) > = > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm= /cpufeature.h > index ad7d26788e6a..8b97cba99fc3 100644 > --- a/arch/riscv/include/asm/cpufeature.h > +++ b/arch/riscv/include/asm/cpufeature.h > @@ -69,12 +69,17 @@ int cpu_online_unaligned_access_init(unsigned int cpu= ); > #if defined(CONFIG_RISCV_SCALAR_MISALIGNED) > void unaligned_emulation_finish(void); > bool unaligned_ctl_available(void); > +bool misaligned_traps_can_delegate(void); > DECLARE_PER_CPU(long, misaligned_access_speed); > #else > static inline bool unaligned_ctl_available(void) > { > return false; > } > +static inline bool misaligned_traps_can_delegate(void) > +{ > + return false; > +} > #endif > = > bool check_vector_unaligned_access_emulated_all_cpus(void); > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/tra= ps_misaligned.c > index db31966a834e..a67a6e709a06 100644 > --- a/arch/riscv/kernel/traps_misaligned.c > +++ b/arch/riscv/kernel/traps_misaligned.c > @@ -716,10 +716,10 @@ static int cpu_online_check_unaligned_access_emulat= ed(unsigned int cpu) > } > #endif > = > -#ifdef CONFIG_RISCV_SBI > - > static bool misaligned_traps_delegated; > = > +#ifdef CONFIG_RISCV_SBI > + > static int cpu_online_sbi_unaligned_setup(unsigned int cpu) > { > if (sbi_fwft_set(SBI_FWFT_MISALIGNED_EXC_DELEG, 1, 0) && > @@ -761,6 +761,7 @@ static int cpu_online_sbi_unaligned_setup(unsigned in= t cpu __always_unused) > { > return 0; > } > + > #endif > = > int cpu_online_unaligned_access_init(unsigned int cpu) > @@ -773,3 +774,15 @@ int cpu_online_unaligned_access_init(unsigned int cp= u) > = > return cpu_online_check_unaligned_access_emulated(cpu); > } > + > +bool misaligned_traps_can_delegate(void) > +{ > + /* > + * Either we successfully requested misaligned traps delegation for all > + * CPUS or the SBI does not implemented FWFT extension but delegated the > + * exception by default. > + */ > + return misaligned_traps_delegated || > + all_cpus_unaligned_scalar_access_emulated(); > +} > +EXPORT_SYMBOL_GPL(misaligned_traps_can_delegate); > \ No newline at end of file Check your editor settings. > -- = > 2.47.2 Reviewed-by: Andrew Jones -- = kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C876B2676E3 for ; Thu, 13 Mar 2025 13:19:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.43 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741871979; cv=none; b=nUuWKq724qeAq9qmTv/KXQX8TUfcKsIAO3h+9T/kPWS1iNqmlU8TohvMZncnnFpNm3wi93KsEj7WSJq/1fA8wK8ybuSWlJk4uU1x1FwsJ1ZOsZ5QLE9oBJI8R3GU452p+kIL8BPsF9g5GKdtf7aXkCDWUmRj+iXAXH/GE9IeDxk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; 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Thu, 13 Mar 2025 06:19:33 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200::59a5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3147ead1dsm81138266b.58.2025.03.13.06.19.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 06:19:33 -0700 (PDT) Date: Thu, 13 Mar 2025 14:19:32 +0100 From: Andrew Jones To: =?utf-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= Cc: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Samuel Holland Subject: Re: [PATCH v3 08/17] riscv: misaligned: add a function to check misalign trap delegability Message-ID: <20250313-4bea400c5770a5a5d3d70b38@orel> References: <20250310151229.2365992-1-cleger@rivosinc.com> <20250310151229.2365992-9-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250310151229.2365992-9-cleger@rivosinc.com> On Mon, Mar 10, 2025 at 04:12:15PM +0100, Clément Léger wrote: > Checking for the delegability of the misaligned access trap is needed > for the KVM FWFT extension implementation. Add a function to get the > delegability of the misaligned trap exception. > > Signed-off-by: Clément Léger > --- > arch/riscv/include/asm/cpufeature.h | 5 +++++ > arch/riscv/kernel/traps_misaligned.c | 17 +++++++++++++++-- > 2 files changed, 20 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h > index ad7d26788e6a..8b97cba99fc3 100644 > --- a/arch/riscv/include/asm/cpufeature.h > +++ b/arch/riscv/include/asm/cpufeature.h > @@ -69,12 +69,17 @@ int cpu_online_unaligned_access_init(unsigned int cpu); > #if defined(CONFIG_RISCV_SCALAR_MISALIGNED) > void unaligned_emulation_finish(void); > bool unaligned_ctl_available(void); > +bool misaligned_traps_can_delegate(void); > DECLARE_PER_CPU(long, misaligned_access_speed); > #else > static inline bool unaligned_ctl_available(void) > { > return false; > } > +static inline bool misaligned_traps_can_delegate(void) > +{ > + return false; > +} > #endif > > bool check_vector_unaligned_access_emulated_all_cpus(void); > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c > index db31966a834e..a67a6e709a06 100644 > --- a/arch/riscv/kernel/traps_misaligned.c > +++ b/arch/riscv/kernel/traps_misaligned.c > @@ -716,10 +716,10 @@ static int cpu_online_check_unaligned_access_emulated(unsigned int cpu) > } > #endif > > -#ifdef CONFIG_RISCV_SBI > - > static bool misaligned_traps_delegated; > > +#ifdef CONFIG_RISCV_SBI > + > static int cpu_online_sbi_unaligned_setup(unsigned int cpu) > { > if (sbi_fwft_set(SBI_FWFT_MISALIGNED_EXC_DELEG, 1, 0) && > @@ -761,6 +761,7 @@ static int cpu_online_sbi_unaligned_setup(unsigned int cpu __always_unused) > { > return 0; > } > + > #endif > > int cpu_online_unaligned_access_init(unsigned int cpu) > @@ -773,3 +774,15 @@ int cpu_online_unaligned_access_init(unsigned int cpu) > > return cpu_online_check_unaligned_access_emulated(cpu); > } > + > +bool misaligned_traps_can_delegate(void) > +{ > + /* > + * Either we successfully requested misaligned traps delegation for all > + * CPUS or the SBI does not implemented FWFT extension but delegated the > + * exception by default. > + */ > + return misaligned_traps_delegated || > + all_cpus_unaligned_scalar_access_emulated(); > +} > +EXPORT_SYMBOL_GPL(misaligned_traps_can_delegate); > \ No newline at end of file Check your editor settings. > -- > 2.47.2 Reviewed-by: Andrew Jones From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4CC52C282DE for ; Thu, 13 Mar 2025 14:36:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Thu, 13 Mar 2025 06:19:33 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200::59a5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3147ead1dsm81138266b.58.2025.03.13.06.19.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 06:19:33 -0700 (PDT) Date: Thu, 13 Mar 2025 14:19:32 +0100 From: Andrew Jones To: =?utf-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= Cc: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Samuel Holland Subject: Re: [PATCH v3 08/17] riscv: misaligned: add a function to check misalign trap delegability Message-ID: <20250313-4bea400c5770a5a5d3d70b38@orel> References: <20250310151229.2365992-1-cleger@rivosinc.com> <20250310151229.2365992-9-cleger@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250310151229.2365992-9-cleger@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250313_061935_822117_373E4687 X-CRM114-Status: GOOD ( 19.27 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Mar 10, 2025 at 04:12:15PM +0100, Cl=E9ment L=E9ger wrote: > Checking for the delegability of the misaligned access trap is needed > for the KVM FWFT extension implementation. Add a function to get the > delegability of the misaligned trap exception. > = > Signed-off-by: Cl=E9ment L=E9ger > --- > arch/riscv/include/asm/cpufeature.h | 5 +++++ > arch/riscv/kernel/traps_misaligned.c | 17 +++++++++++++++-- > 2 files changed, 20 insertions(+), 2 deletions(-) > = > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm= /cpufeature.h > index ad7d26788e6a..8b97cba99fc3 100644 > --- a/arch/riscv/include/asm/cpufeature.h > +++ b/arch/riscv/include/asm/cpufeature.h > @@ -69,12 +69,17 @@ int cpu_online_unaligned_access_init(unsigned int cpu= ); > #if defined(CONFIG_RISCV_SCALAR_MISALIGNED) > void unaligned_emulation_finish(void); > bool unaligned_ctl_available(void); > +bool misaligned_traps_can_delegate(void); > DECLARE_PER_CPU(long, misaligned_access_speed); > #else > static inline bool unaligned_ctl_available(void) > { > return false; > } > +static inline bool misaligned_traps_can_delegate(void) > +{ > + return false; > +} > #endif > = > bool check_vector_unaligned_access_emulated_all_cpus(void); > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/tra= ps_misaligned.c > index db31966a834e..a67a6e709a06 100644 > --- a/arch/riscv/kernel/traps_misaligned.c > +++ b/arch/riscv/kernel/traps_misaligned.c > @@ -716,10 +716,10 @@ static int cpu_online_check_unaligned_access_emulat= ed(unsigned int cpu) > } > #endif > = > -#ifdef CONFIG_RISCV_SBI > - > static bool misaligned_traps_delegated; > = > +#ifdef CONFIG_RISCV_SBI > + > static int cpu_online_sbi_unaligned_setup(unsigned int cpu) > { > if (sbi_fwft_set(SBI_FWFT_MISALIGNED_EXC_DELEG, 1, 0) && > @@ -761,6 +761,7 @@ static int cpu_online_sbi_unaligned_setup(unsigned in= t cpu __always_unused) > { > return 0; > } > + > #endif > = > int cpu_online_unaligned_access_init(unsigned int cpu) > @@ -773,3 +774,15 @@ int cpu_online_unaligned_access_init(unsigned int cp= u) > = > return cpu_online_check_unaligned_access_emulated(cpu); > } > + > +bool misaligned_traps_can_delegate(void) > +{ > + /* > + * Either we successfully requested misaligned traps delegation for all > + * CPUS or the SBI does not implemented FWFT extension but delegated the > + * exception by default. > + */ > + return misaligned_traps_delegated || > + all_cpus_unaligned_scalar_access_emulated(); > +} > +EXPORT_SYMBOL_GPL(misaligned_traps_can_delegate); > \ No newline at end of file Check your editor settings. > -- = > 2.47.2 Reviewed-by: Andrew Jones _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv