From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Gregory Price <gourry@gourry.net>
Cc: Yuquan Wang <wangyuquan1236@phytium.com.cn>,
<lsf-pc@lists.linux-foundation.org>, <linux-mm@kvack.org>,
<linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [LSF/MM] CXL Boot to Bash - Section 0: ACPI and Linux Resources
Date: Thu, 13 Mar 2025 17:00:51 +0000 [thread overview]
Message-ID: <20250313170051.0000267e@huawei.com> (raw)
In-Reply-To: <Z8sM-W1F6-TIZcGa@gourry-fedora-PF4VCD3F>
On Fri, 7 Mar 2025 10:12:57 -0500
Gregory Price <gourry@gourry.net> wrote:
> On Fri, Mar 07, 2025 at 10:20:31AM +0800, Yuquan Wang wrote:
> > > 2a) Is the BIOS programming decoders, or are you programming the
> > > decoder after boot?
> > Program the decoder after boot. It seems like currently bios for qemu could
> > not programm cxl both on x86(q35) and arm64(virt). I am trying to find a
> > cxl-enable bios for qemu virt to do some test.
>
> What's likely happening here then is that QEMU is not emitting an SRAT
> (either because the logic is missing or by design).
>
> From other discussions, this may be the intention of the GenPort work,
> which is intended to have placeholders in the SRAT for the Proximity
> Domains for devices to be initialized later (i.e. dynamically).
>
For QEMU you need to provide a whole bunch of config to get SRAT / HMAT
etc ( and BIOS never configures the stuff, it's all OS first.
I wrote a slightly pathological test case that should give the general idea
https://elixir.bootlin.com/qemu/v9.2.2/source/tests/qtest/bios-tables-test.c#L1940
It flushed out a few bugs :)
test_acpi_one(" -machine hmat=on,cxl=on"
" -smp 3,sockets=3"
" -m 128M,maxmem=384M,slots=2"
" -device pcie-root-port,chassis=1,id=pci.1"
" -device pci-testdev,bus=pci.1,"
"multifunction=on,addr=00.0"
" -device pci-testdev,bus=pci.1,addr=00.1"
" -device pci-testdev,bus=pci.1,id=gidev,addr=00.2"
" -device pxb-cxl,bus_nr=64,bus=pcie.0,id=cxl.1"
" -object memory-backend-ram,size=64M,id=ram0"
" -object memory-backend-ram,size=64M,id=ram1"
" -numa node,nodeid=0,cpus=0,memdev=ram0"
" -numa node,nodeid=1"
" -object acpi-generic-initiator,id=gi0,pci-dev=gidev,node=1"
" -numa node,nodeid=2"
" -object acpi-generic-port,id=gp0,pci-bus=cxl.1,node=2"
" -numa node,nodeid=3,cpus=1"
" -numa node,nodeid=4,memdev=ram1"
" -numa node,nodeid=5,cpus=2"
" -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
"data-type=access-latency,latency=10"
" -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
"data-type=access-bandwidth,bandwidth=800M"
" -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
"data-type=access-latency,latency=100"
" -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
"data-type=access-bandwidth,bandwidth=200M"
" -numa hmat-lb,initiator=0,target=4,hierarchy=memory,"
"data-type=access-latency,latency=100"
" -numa hmat-lb,initiator=0,target=4,hierarchy=memory,"
"data-type=access-bandwidth,bandwidth=200M"
" -numa hmat-lb,initiator=0,target=5,hierarchy=memory,"
"data-type=access-latency,latency=200"
" -numa hmat-lb,initiator=0,target=5,hierarchy=memory,"
"data-type=access-bandwidth,bandwidth=400M"
" -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
"data-type=access-latency,latency=500"
" -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
"data-type=access-bandwidth,bandwidth=100M"
" -numa hmat-lb,initiator=1,target=2,hierarchy=memory,"
"data-type=access-latency,latency=50"
" -numa hmat-lb,initiator=1,target=2,hierarchy=memory,"
"data-type=access-bandwidth,bandwidth=400M"
" -numa hmat-lb,initiator=1,target=4,hierarchy=memory,"
"data-type=access-latency,latency=50"
" -numa hmat-lb,initiator=1,target=4,hierarchy=memory,"
"data-type=access-bandwidth,bandwidth=800M"
" -numa hmat-lb,initiator=1,target=5,hierarchy=memory,"
"data-type=access-latency,latency=500"
" -numa hmat-lb,initiator=1,target=5,hierarchy=memory,"
"data-type=access-bandwidth,bandwidth=100M"
" -numa hmat-lb,initiator=3,target=0,hierarchy=memory,"
"data-type=access-latency,latency=20"
" -numa hmat-lb,initiator=3,target=0,hierarchy=memory,"
"data-type=access-bandwidth,bandwidth=400M"
" -numa hmat-lb,initiator=3,target=2,hierarchy=memory,"
"data-type=access-latency,latency=80"
" -numa hmat-lb,initiator=3,target=2,hierarchy=memory,"
"data-type=access-bandwidth,bandwidth=200M"
" -numa hmat-lb,initiator=3,target=4,hierarchy=memory,"
"data-type=access-latency,latency=80"
" -numa hmat-lb,initiator=3,target=4,hierarchy=memory,"
"data-type=access-bandwidth,bandwidth=200M"
" -numa hmat-lb,initiator=3,target=5,hierarchy=memory,"
"data-type=access-latency,latency=20"
" -numa hmat-lb,initiator=3,target=5,hierarchy=memory,"
"data-type=access-bandwidth,bandwidth=400M"
" -numa hmat-lb,initiator=5,target=0,hierarchy=memory,"
"data-type=access-latency,latency=20"
" -numa hmat-lb,initiator=5,target=0,hierarchy=memory,"
"data-type=access-bandwidth,bandwidth=400M"
" -numa hmat-lb,initiator=5,target=2,hierarchy=memory,"
"data-type=access-latency,latency=80"
" -numa hmat-lb,initiator=5,target=4,hierarchy=memory,"
"data-type=access-bandwidth,bandwidth=200M"
" -numa hmat-lb,initiator=5,target=4,hierarchy=memory,"
"data-type=access-latency,latency=80"
" -numa hmat-lb,initiator=5,target=2,hierarchy=memory,"
"data-type=access-bandwidth,bandwidth=200M"
" -numa hmat-lb,initiator=5,target=5,hierarchy=memory,"
"data-type=access-latency,latency=10"
" -numa hmat-lb,initiator=5,target=5,hierarchy=memory,"
"data-type=access-bandwidth,bandwidth=800M",
&data);
Jonathan
> ~Gregory
>
next prev parent reply other threads:[~2025-03-13 17:00 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-26 20:19 [LSF/MM] Linux management of volatile CXL memory devices - boot to bash Gregory Price
2025-02-05 2:17 ` [LSF/MM] CXL Boot to Bash - Section 1: BIOS, EFI, and Early Boot Gregory Price
2025-02-18 10:12 ` Yuquan Wang
2025-02-18 16:11 ` Gregory Price
2025-02-20 16:30 ` Jonathan Cameron
2025-02-20 16:52 ` Gregory Price
2025-03-04 0:32 ` Gregory Price
2025-03-13 16:12 ` Jonathan Cameron
2025-03-13 17:20 ` Gregory Price
2025-03-10 10:45 ` Yuquan Wang
2025-03-10 14:19 ` Gregory Price
2025-02-05 16:06 ` CXL Boot to Bash - Section 2: The Drivers Gregory Price
2025-02-06 0:47 ` Dan Williams
2025-02-06 15:59 ` Gregory Price
2025-03-04 1:32 ` Gregory Price
2025-03-06 23:56 ` CXL Boot to Bash - Section 2a (Drivers): CXL Decoder Programming Gregory Price
2025-03-07 0:57 ` Zhijian Li (Fujitsu)
2025-03-07 15:07 ` Gregory Price
2025-03-11 2:48 ` Zhijian Li (Fujitsu)
2025-04-02 6:45 ` Zhijian Li (Fujitsu)
2025-04-02 14:18 ` Gregory Price
2025-04-08 3:10 ` Zhijian Li (Fujitsu)
2025-04-08 4:14 ` Gregory Price
2025-04-08 5:37 ` Zhijian Li (Fujitsu)
2025-02-17 20:05 ` CXL Boot to Bash - Section 3: Memory (block) Hotplug Gregory Price
2025-02-18 16:24 ` David Hildenbrand
2025-02-18 17:03 ` Gregory Price
2025-02-18 17:49 ` Yang Shi
2025-02-18 18:04 ` Gregory Price
2025-02-18 19:25 ` David Hildenbrand
2025-02-18 20:25 ` Gregory Price
2025-02-18 20:57 ` David Hildenbrand
2025-02-19 1:10 ` Gregory Price
2025-02-19 8:53 ` David Hildenbrand
2025-02-19 16:14 ` Gregory Price
2025-02-20 17:50 ` Yang Shi
2025-02-20 18:43 ` Gregory Price
2025-02-20 19:26 ` David Hildenbrand
2025-02-20 19:35 ` Gregory Price
2025-02-20 19:44 ` David Hildenbrand
2025-02-20 20:06 ` Gregory Price
2025-03-11 14:53 ` Zi Yan
2025-03-11 15:58 ` Gregory Price
2025-03-11 16:08 ` Zi Yan
2025-03-11 16:15 ` Gregory Price
2025-03-11 16:35 ` Oscar Salvador
2025-03-05 22:20 ` [LSF/MM] CXL Boot to Bash - Section 0: ACPI and Linux Resources Gregory Price
2025-03-05 22:44 ` Dave Jiang
2025-03-05 23:34 ` Gregory Price
2025-03-05 23:41 ` Dave Jiang
2025-03-06 0:09 ` Gregory Price
2025-03-06 1:37 ` Yuquan Wang
2025-03-06 17:08 ` Gregory Price
2025-03-07 2:20 ` Yuquan Wang
2025-03-07 15:12 ` Gregory Price
2025-03-13 17:00 ` Jonathan Cameron [this message]
2025-03-08 3:23 ` [LSF/MM] CXL Boot to Bash - Section 0a: CFMWS and NUMA Flexiblity Gregory Price
2025-03-13 17:20 ` Jonathan Cameron
2025-03-13 18:17 ` Gregory Price
2025-03-14 11:09 ` Jonathan Cameron
2025-03-14 13:46 ` Gregory Price
2025-03-13 16:55 ` [LSF/MM] CXL Boot to Bash - Section 0: ACPI and Linux Resources Jonathan Cameron
2025-03-13 17:30 ` Gregory Price
2025-03-14 11:14 ` Jonathan Cameron
2025-03-27 9:34 ` Yuquan Wang
2025-03-27 12:36 ` Gregory Price
2025-03-27 13:21 ` Dan Williams
2025-03-27 16:36 ` Gregory Price
2025-03-31 23:49 ` [Lsf-pc] " Dan Williams
2025-03-12 0:09 ` [LSF/MM] CXL Boot to Bash - Section 4: Interleave Gregory Price
2025-03-13 8:31 ` Yuquan Wang
2025-03-13 16:48 ` Gregory Price
2025-03-26 9:28 ` Yuquan Wang
2025-03-26 12:53 ` Gregory Price
2025-03-27 2:20 ` Yuquan Wang
2025-03-27 2:51 ` [Lsf-pc] " Dan Williams
2025-03-27 6:29 ` Yuquan Wang
2025-03-14 3:21 ` [LSF/MM] CXL Boot to Bash - Section 6: Page allocation Gregory Price
2025-03-18 17:09 ` [LSFMM] Updated: Linux Management of Volatile CXL Memory Devices Gregory Price
2025-04-02 4:49 ` Gregory Price
2025-04-07 16:14 ` Adam Manzanares
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250313170051.0000267e@huawei.com \
--to=jonathan.cameron@huawei.com \
--cc=gourry@gourry.net \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mm@kvack.org \
--cc=lsf-pc@lists.linux-foundation.org \
--cc=wangyuquan1236@phytium.com.cn \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.