From: Zenghui Yu <zenghui.yu@linux.dev>
To: qemu-devel@nongnu.org, qemu-arm@nongnu.org
Cc: agraf@csgraf.de, peter.maydell@linaro.org,
Zenghui Yu <zenghui.yu@linux.dev>
Subject: [PATCH] hvf: arm: Emulate ICC_RPR_EL1 accesses properly
Date: Sat, 15 Mar 2025 21:20:30 +0800 [thread overview]
Message-ID: <20250315132030.95209-1-zenghui.yu@linux.dev> (raw)
Commit a2260983c655 ("hvf: arm: Add support for GICv3") added GICv3 support
by implementing emulation for a few system registers. ICC_RPR_EL1 was
defined but not plugged in the sysreg handlers (for no good reason).
Fix it.
Signed-off-by: Zenghui Yu <zenghui.yu@linux.dev>
---
target/arm/hvf/hvf.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 87e35c1b71..650b7f4256 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -1359,6 +1359,7 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val)
case SYSREG_ICC_IGRPEN0_EL1:
case SYSREG_ICC_IGRPEN1_EL1:
case SYSREG_ICC_PMR_EL1:
+ case SYSREG_ICC_RPR_EL1:
case SYSREG_ICC_SGI0R_EL1:
case SYSREG_ICC_SGI1R_EL1:
case SYSREG_ICC_SRE_EL1:
@@ -1673,6 +1674,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
case SYSREG_ICC_IGRPEN0_EL1:
case SYSREG_ICC_IGRPEN1_EL1:
case SYSREG_ICC_PMR_EL1:
+ case SYSREG_ICC_RPR_EL1:
case SYSREG_ICC_SGI0R_EL1:
case SYSREG_ICC_SGI1R_EL1:
case SYSREG_ICC_SRE_EL1:
--
2.34.1
next reply other threads:[~2025-03-15 13:21 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-15 13:20 Zenghui Yu [this message]
2025-03-18 16:56 ` [PATCH] hvf: arm: Emulate ICC_RPR_EL1 accesses properly Peter Maydell
2025-03-20 16:55 ` Zenghui Yu
2025-06-22 8:56 ` Zenghui Yu
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