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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1ffbcef5sm104115665e9.9.2025.03.17.06.16.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 06:16:27 -0700 (PDT) Date: Mon, 17 Mar 2025 13:16:23 +0000 From: David Laight To: Linus Torvalds Cc: "Herton R. Krzesinski" , x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, linux-kernel@vger.kernel.org, olichtne@redhat.com, atomasov@redhat.com, aokuliar@redhat.com Subject: Re: [PATCH] x86: add back the alignment of the destination to 8 bytes in copy_user_generic() Message-ID: <20250317131623.2cc15ada@pumpkin> In-Reply-To: References: <20250314175309.2263997-1-herton@redhat.com> <20250314175309.2263997-2-herton@redhat.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Fri, 14 Mar 2025 09:06:13 -1000 Linus Torvalds wrote: > On Fri, 14 Mar 2025 at 07:53, Herton R. Krzesinski wrote: > > > > --- a/arch/x86/include/asm/uaccess_64.h > > +++ b/arch/x86/include/asm/uaccess_64.h > > @@ -130,7 +130,7 @@ copy_user_generic(void *to, const void *from, unsigned long len) > > "2:\n" > > _ASM_EXTABLE_UA(1b, 2b) > > :"+c" (len), "+D" (to), "+S" (from), ASM_CALL_CONSTRAINT > > - : : "memory", "rax"); > > + : : "memory", "rax", "rdx", "r8"); > > Please don't penalize the caller with the extra clobbers. > > Maybe it doesn't matter - these functions are marked always_inline, > but they aren't inlined in very many places and maybe those places > have registers to spare - but let's not penalize the FSRM case anyway. > > And we do call it "rep_movs_alternative", so let's keep it close to > "rep movs" semantics (yes, we already clobber %rax, but let's not make > it worse). > > As to the actual change to rep_movs - that should be done differently > too. In particular, I doubt it makes any sense to try to align the > destination for small writes or for the ERMS case when we use 'rep > movsb', so I think this should all go into just the ".Llarge_movsq" > case. The Intel cpu (sandy bridge onwards) execute 'rep mosvb' twice as fast if the destination is 32 byte aligned. Potentially this is worth optimising for - but the cost of the extra code may exceed the benefit. > .. and then the patch can be further optimized to just do the first - > possibly unaligned - destination word unconditionally, and then > updating the addresses and counts to make the rest be aligned. You can also something similar for any trailing bytes. If you are feeling 'brave' copy the last 8 bytes first. David